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25 mhz to 3000 mhz fractional - n pll with integrated vco data sheet HMC832A rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result f rom its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one te chnology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com features rf b andwidth: 25 mhz to 3000 mhz 3.3 v s upply maximum phase detector rate: 100 mhz ultral ow phase noise ? 110 dbc/hz in b and ( typical ) , f o at 1600 mhz fractional figure of merit (fom) : ? 226 dbc/hz 24 - bit step size , 3 hz typical resolution exact fre quency mode with 0 hz frequency error fast frequency hopping 40 - l ead , 6 mm 6 mm lfcsp p ackage: 36 mm 2 applications cellular i nfrastructure microwave r adio s wimax, wifi communications test equipment c at v e quipment dds r eplacement military tunable referenc e source s for spurious - free performance functional block dia gram figure 1. general description the HMC832A is a 3.3 v, high performance, wide band, f rac - tional - n , ph ase - locked loop (pll) that features an integrated voltage controlled oscillator (vco) with a fundamental frequency of 1500 mhz to 3000 mhz and an integrated vco output divider (divide by 1 , 2 , 4 , 6 , 62) that enables the HMC832A to generate continuous frequencies from 25 mhz to 3000 mhz. the integrated phase detector (pd) and - m odulator, capable of operating at up to 100 mhz, permit wider loop bandwidths and faster frequency tuning with excellent spectral performance. industry leading phase noise and spurious performance, across all frequencies, enable the HMC832A to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. a l ow noise floor ( ? 160 dbc/hz eliminates any contri bution to modulator/mixer noise floor in transmitter applications. the HMC832A is footprint compatible to the hmc830 pll with an integrated vco. it features 3.3 v supply and inn ovative p rogrammable perfor mance technology that enables the HMC832A to tailor current consumption and corresponding noise floor performance to individual applica tions by selecting either a low current consumption mode or a high performance mode for improved noise floor performance. additional features of the HMC832A include 12 db of rf output gain control in 1 db steps; an output m ute functio n to automatically mute the output during frequency changes when the device is not locked; selectable output return loss; p rogrammable differential or single - ended outputs, with the ability to select either output in single - ended mode; a - modulator exact frequency mode that enables users to generate output frequencies with 0 hz frequency error; and a r egister configurable 3.3 v or 1.8 v s erial port i nterface (spi) . cp en en vtune rf_n rf_p sen cp pfd r n 1, 2, 4, 6, ...62 modul a t or xrefp ld/sdo sck sdi cal vco lock detect HMC832A spi programming inter f ace control 13 1 10-001
HMC832A data sheet rev. b | page 2 of 48 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 6 absolute maximum ratings ............................................................ 7 recommended operating conditions ...................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical p erformance characteristics ............................................. 9 theory of operation ...................................................................... 15 pll subsystem overview .......................................................... 15 vco subsystem overview ........................................................ 15 spi configuration of pll and vco subsystems ................... 15 vco subsystem .......................................................................... 17 pll subsystem ............................................................................ 21 soft reset and power - on reset ................................................ 28 power - down mode .................................................................... 28 general - purpose output (gpo) .............................................. 28 chip identification ..................................................................... 29 serial port interface (spi) .......................................................... 29 applications information .............................................................. 32 power supply ............................................................................... 33 programmable performance technology ................................ 33 loop filter and frequency changes ........................................ 33 rf programmable output return loss ................................... 34 mute mode .................................................................................. 34 pll register map ........................................................................... 35 id, read address, and reset (rst) registers ........................ 35 reference divider (refdiv), integer, and fractional frequency registers ................................................................... 35 vco spi register ....................................................................... 36 - configuration register ...................................................... 36 lock detect register .................................................................. 37 analog enable (en) register .................................................... 37 charge pump register ............................................................... 38 autocalibration register ............................................................ 38 phase detector (pd) register ................................................... 39 exact frequency mode register ............................................... 39 general - purpose, spi, and reference divider (gpo_spi_rdiv) register ...................................................... 40 vco tune register .................................................................... 41 sucessive approximation register ........................................... 41 general - purpose 2 register ...................................................... 41 built - in self test (bist) register ............................................. 41 vco subsystem register map ...................................................... 42 vco enable register ................................................................. 42 vco output divider register .................................................. 43 vco configuration register .................................................... 43 vco calibration/bias, center frequency calibration (cf_cal), and msb calibration registers ............................ 44 vco output power control ..................................................... 44 evaluation printed circuit board (pcb) ..................................... 45 changing evaluation board reference frequency and cp current configuration .............................................................. 46 evaluation kit contents ............................................................ 46 outline dimensions ....................................................................... 47 ordering guide .......................................................................... 48 revision history 11/1 5 rev ision b: initial version
data sheet HMC832A rev. b | page 3 of 48 specificat ions vp pcp, vddls, vcc1, vcc2, rvdd, avdd, dvdd, vccpd, vcchf, vccps = 3.3 v m in imum and m ax imum s pecified across the t emp erature range of ? 40c to + 85 c. table 1 . parameter rf output ch aracteristics output frequency 25 3000 mhz vco frequency at pll input 1500 3000 mhz rf output frequency at f vco 1500 3000 mhz output power rf output power a cross all frequencies (see figure 25 ) , h igh p erformance m ode (vco_reg 0x03[1:0] = 3 d ) max imum gain setting ( vco_reg 0x07 [3:0] = 0xb) , single - ended 7 dbm gain setting 6 ( vco_reg 0x07 [3:0] = 6 d ) , differential 2 dbm output power control r ange 1 db steps 12 db harmonics for funda mental mode f o mode at 2 ghz second/third/fourth harmonics ? 20/?29/?45 dbc f o /2 mode at 2 ghz/ 2 = 1 ghz second/third/fourth harmonics ? 26/?10/?34 dbc f o / 30 mode at 3 ghz/ 30 = 100 mhz second/third/fourth harmonics ? 33/?10/?40 dbc f o /62 mode at 1550 mhz/ 62 = 25 mhz second/third/fourth harmonics ? 40/?6 /?43 dbc vco output divider vco rf divider range 1 , 2 , 4 , 6 , 8 , 62 1 62 pll rf divider characteristics 19 - bit n - divider range (integer) max imum = 2 19 ? 1 16 524,287 ( ( ( ( dc 100 mhz pd frequency integer mode dc 100 mhz charge pump output current 0.02 / ( / / / input voltage low ( v il ) 0.75 v high ( v ih ) 1.15 v sck clock frequency rate 6 50 mhz
HMC832A data sheet rev. b | page 4 of 48 parameter ld/sdo logic output output high voltage high (v oh ) cmos 1.8 v m ode (register 0x0f[9:8] = 00b, register 0x0b[22] = 0) 1.3 2.3 v cmos 3.3 v m ode (register 0x0f[9:8] = 00b, register 0x0b[22] = 1 ) v dd ? 0.2 v dd v open -d rain m ode (register 0x 0f[9:8] = 01b) 4 1.8 v low (v ol ) cmos m ode (register 0x0f[9:8] = 00b) 0.1 v open - drain mode (register 0x0f[9:8] = 01b) 5 0.4 sck clock frequency rate cmos m ode (register0x0f[9:8] = 00b) 6 6 50 mhz open - drain mode (register0x0f[9:8] = 01b) 7 5 10 mhz capacitive load cmos m ode (register0x0f[9:8] = 00b) 10 20 pf open - drain mode (register0x0f[9:8] = 01b) 8 10 pf load current cmos m ode (register0x0f[9:8] = 00b) 9 3.6 ma open - drain mode (register0x0f[9:8] = 01b) 10 7.2 ma output resistance wh en driver is low (r on ) open - drain mode (register0x0f[9:8] = 01b) 100 200 pull - up resistor (r up ) open - drain mode (register0x0f[9:8] = 01b) 500 1000 rise time cmos m ode (register0x0f[9:8] = 00b) 11 0.5 + 0.3( c load ) 7 ns fall time cmos m ode (register0 x0f[9:8] = 00b) 11 1 .5 + 0.2( c load ) 10 ns sck to sdo turn a round time cmos m ode (register0x0f[9:8] = 00b) 11 0.9 + 0.1( c load ) 12 ns output impedance (r out ) 1.8 v m ode (register 0x0b[22] = 0 ) 100 200 power supply voltages 3.3 v supplies avdd, vcchf, vccps, vccpd, rvdd, dvdd, vppcp, vddls, vcc 1 , vcc 2 3.1 ( ( ( ( ( ( ( ( ( ( /
data sheet HMC832A rev. b | page 5 of 48 parameter vco ope n - loop phase noise f o at 2 ghz 13 10 khz offset ? 88 dbc/hz 100 khz offset ? 116 dbc/hz 1 mhz offset ? 139 dbc/hz 10 mhz offset ? 157 dbc/hz 100 mhz offset ? 162 dbc/hz f o at 2 ghz/2 = 1 ghz 13 10 khz offset ? 93 dbc/hz 100 khz offset ? 122 dbc/hz 1 mhz offset ? 145 dbc/hz 10 mhz offset ? 159 dbc/hz 100 mhz offset ? 162 dbc/hz f o at 3 ghz/30 = 100 mhz 13 10 khz offse t ? 110 dbc/hz 100 khz offset ? 139 dbc/hz 1 mhz offset ? 160 dbc/hz 10 mhz offset ? 163 dbc/hz 100 mhz offset ? 163 dbc/hz 250 k hz o ffset f o 13 over manufacturing process variations with 3 .3 v power supply at 25c f o = 1584 mhz ? 124.5 dbc/hz f o = 1998 mhz ? 122.5 dbc/hz f o = 2416 mhz ? 122.0 dbc/hz f o = 2812 mhz ? 121.0 dbc/hz pll phase noise at 20 khz offset, 50 mhz pfd rate over process with 3.3 v power supply at 2 5 c, m easured with >200 k hz loop bandwidth f o = 1582.896 mhz ? 113.5 dbc/hz f o = 1998.25 mhz ? 113.5 dbc/hz f o = 2415.735 mhz ? 112.5 dbc/hz f o = 2811.21 mhz ? 109.5 dbc/hz lock time depends on loop filter bandwidth, pfd rate , and definit ion of lock (to within hz or degrees of settling) 500 s frequency resolution depends on pfd rate and vco o utput d ivider setting fundamental mode 1.5 ghz to 3 ghz output ; at typical phase detector frequency (f pd ) of 50 mhz, typical resolution = 3 hz f pd /2 24 hz divider mode <1.5 ghz output , r esolution depend s on vco output divider setting f pd /(2 24 output divider) hz reference spurs ? 85 dbc/hz figure of merit (fom) normalized to 1 hz (see figure 24 ) floor integer mode ? 229 dbc/hz floor fractional mode ? 226 dbc/hz flicker (both modes) ? 268 dbc/hz
HMC832A data sheet rev. b | page 6 of 48 parameter vco characteristics vc o tuning sensitivity measured with 1.5 v on vtune (see figure 29) 2800 mhz 24.6 mhz/v 2400 mhz 25.8 mhz/v 2000 mhz 25.2 mhz/v 1600 mhz 24.3 mhz/v vco supply pushing 14 measured with 1.5 v on vt une 2.8 mhz/v 1 measured with 100 external termination. see the reference input stage section for more details. 2 slew rate o f 0.5 ns/v is recommended . s ee the reference input stage section for more details. frequency is guaranteed across process voltage and temperature from ?40c to +85c. 3 this maximum pd frequency can only be achiev ed if the minimum n value is respected. for example, in the case of fractional mode, the maximum pd frequency = f vco /20 or 100 mhz, whichever is less. 4 external 1 k pull - up resistor to 1.8 v. 5 limited by the 1 k pull - up resistor and nmos r on . 6 10 pf l oad capacitor. 7 10 pf load capacitor, 1 k pull - up resistor. in general, open - drain mode can support higher frequencies at the expense of maximum v ol . the maximum frequency for a given pull - up resistor and load capacitor is approximately 1/(10 r pull - up c load ). for example, a 10 pf load capacitor and 1 k pull - up resistor can support up to 10 mhz, where v ol maximum = v dd r on /( 1 k + r on ) 164 mv. with a 500 pull - up resistance and a 10 pf load, a 20 mhz maximum frequency is possible, and the maximum v ol increases to 300 mv. 8 1 k pull - up resistor. 9 the minimum resistive load to ground in cmos mode is 1 k. 10 the ld/sdo pin does not have short - circuit protection. the maximum current of 7.2 ma must not be exceeded under any condition. 11 c load in pf. c load maximum = 20 pf. 12 for detailed current consumption information, refer to figure 33 and figure 36 . 13 gain setting = 6 (vco_reg 0x07[3:0] = 6d) in high performance mod e (vco_reg 0x03[1:0] = 3d). 14 pushing refers to a change in vco frequency due to a change in the power supply voltage. timing specification s spi write timing characteristics avdd = dvdd = 3 v, exposed pad (ep) = 0 v . see figure 47. table 2 . parameter test conditions /comments min typ max u nit t 1 sdi setup time to sc k rising edge 3 ns t 2 sc k rising edge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 sc k 32 nd rising edge to sen rising edge 10 ns t 6 recovery time 20 ns f sck maximum serial port clock speed 50 mhz spi read timing characteristics avdd = dvdd = 3 v, exposed pad (ep) = 0 v. see figure 48. table 3 . parameter test conditions /comments min typ max unit t 1 sdi setup tim e to sck r ising e dge 3 ns t 2 sck rising edge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 1 sck rising edge to sdo time 8.2 ns + 0.2 ns/pf ns t 6 recovery time 10 ns t 7 sck 32 nd rising edge to sen rising ed ge 10 ns 1 an extra 0.2 ns delay is required for every 1 pf load on sdo.
data sheet HMC832A rev. b | page 7 of 48 absolute maximum rat ings table 4 . parameter rating avdd, rvdd, dvdd, vccpd, vcchf, vccps ( ( / ( stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress ratin g only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product re liability. r ecommended operating conditions table 5 . recommended operating conditions parameter min typ max unit temperature junction temperature 1 125 c ambient temperature ? 40 + 85 c supply voltage avdd, rvdd, dvdd , vccpd, vcchf, vccps, vppcp, vddls, vcc 1 , vcc 2 3.1 3.3 3.5 v 1 using the l ayout design guid e lines set out in the qualification test report is strongly recommended. esd cautio n
HMC832A data sheet rev. b | page 8 of 48 pin configuration an d function descripti ons figure 2 . pin configuration table 6 . pin function descriptions pin number 1 avdd dc power supply for analog circuitry . 2, 5, 6 , 8, 9, 11 to 14, 18 to 22 , 24, 26, 34, 37, 38 n i c no t internally connect ed . the se pins are not connected internally; however , i t is recommended to connect these pins to rf/ dc ground externally. 3 vppcp power supply for the charge pump analog section . 4 cp charge pump output . 7 vddls power supply for the charge pump digital section . 10 rvdd reference supply . 15 xrefp reference oscillator input . 16 dvdd dc power supply for digital (cmos) circuitry . 17 cen pll subsystem enable . note that cen has n o eff ect on the vco subsystem . connect cen to logic high for normal operation. 23 vtune vco varactor. vtune is the t uning port input . 25 vcc 2 vco analog supply 2 . 27 vcc 1 vco analog supply 1 . 28 rf_n rf negative output . 29 rf_p rf positive output . 30 sen pll serial port enable (cmos) logic input . 31 sdi pll serial port data (cmos) logic input . 32 sck pll serial port clock (cmos) logic input . 33 ld/sdo lock detect / serial data output. this pin can also function as a g eneral -p urpose (cmos) l ogic o utput (gp o) . see the general - purpose output (gpo) section for more information. the drive voltage level on this pin can be either 1.8 v or 3.3 v and is set via register 0x0b[22]. 35 vcchf dc power supply for analog circui try . 36 vccps dc power supply for analog prescaler . 39 vccpd dc power supply for phase detector . 40 bias external bypass decoupling for precision bias circuits . the 1.920 v 20 mv reference voltage (bias) is generated internally and cannot drive an ext ernal load. it m ust be measured with a 10 g meter , such as the agilent 34410a ; a 10 m digital voltage meter read s erroneously. ep exposed pad. the exposed pad must be connected to rf/dc ground. notes 1. nic = not internal l y connected. 2. the exposed ground p ad must be connected t o rf/dc ground. 1 a vdd 2 nic 3 vppcp 4 cp 5 nic 6 nic 7 vddls 8 nic 9 nic 10 r vdd 23 vtune 24 nic 25 vcc2 26 nic 27 vcc1 28 rf_n 29 rf_p 30 sen 22 nic 21 nic 1 1 2 1 3 1 5 1 7 1 6 1 8 1 9 1 0 2 4 1 nic 3 3 4 3 5 3 6 3 7 3 8 3 9 3 0 4 2 3 1 3 bias HMC832A t o p view (not to scale) 13 1 10-002 nic nic nic xref p dvdd cen nic nic nic vccpd nic nic vccps vcchf nic ld/sdo sck sdi
data sheet HMC832A rev. b | page 9 of 48 typical performance characteristics figure 3. typical closed - loop integer phase noise, 50 mhz pd frequency, output gain = 6 (vco_reg 0x07[3:0] = 6d), high performance mode (vco_reg 0x03[1:0] = 3d), phase noise integrated from 1 khz to 100 mhz, see table 13 figure 4 . open - loop vco phase noise at 1800 mhz figure 5 . free running vco phase noise at 3000 mhz figure 6 . typical closed - loop fractional phase noise, 50 mhz pd frequency, output gain = 6 (vco_reg 0x07[3:0] = 6d), high performance mode (vco_reg 0x03[1:0] = 3d), phase noise integrated from 1 khz to 100 mhz, see table 13 figure 7. clos ed - loop phase noise at 1800 mhz, divided by 1 to 62, pd frequency, loop filter bandwidth = 75 khz (type 2 from table 13 ), high perfor - mance mode (vco_reg 0x03[1:0] = 3d), subset of available output divide ratios sh own; full range of output divide values includes 1, 2, 4, 6, 8, 58, 60, 62 figure 8. closed - loop phase noise at 3000 mhz, divided by 1 to 62, pd frequency, loop filter bandwidth = 75 khz (type 2 from table 13 ), high perfor - mance mode (vco_reg 0x03[1:0] = 3d), subset of available output divide ratios is shown; full range of output divide values includes 1, 2, 4, 6, 8, 58, 60, 62 ?170 1k 10k 100k 1m 10m 100m ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 offset (hz) phase noise (dbc/hz) 750mhz, evm = ?62.5db, or 0.075% 1600mhz, evm = ?57db or 0.141% 2500mhz, evm = ?53.3db or 0.216% 875mhz, evm = ?64.8db or 0.058% 1600mhz, evm = ?59.8db or 0.102% 2500mhz, evm = ?55.8db or 0.168% loo p bw = 127khz loo p bw = 75khz 13 1 10-003 1k 10k 100k 1m 10m 100m offset (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) low current mode (vco_reg 0x03[10] = 1d) high performance mode (vco_reg 0x03[10] = 3d) 13 1 10-004 phase noise (dbc/hz) 1k 10k 100k 1m 10m 100m offset (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?40 ?60 low current mode (vco_reg 0x03[10] = 1d) high performance mode (vco_reg 0x03[10] = 3d) 13 1 10-005 ?170 1k 10k 100k 1m 10m 100m ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 offset (hz) phase noise (dbc/hz) loo p bw = 127khz 880mhz, evm = ?61.3db or 0.086% 1605mhz, evm = ?57.5db or 0.133% 2505mhz, evm = ?52db or 0.251% 880mhz, evm = ?61.8db or 0.081% 1605mhz, evm = ?57.2db or 0.138% 2505mhz, evm = ?53.9db or 0.204% loo p bw = 75khz 13 1 10-006 1k 10k 100k 1m 10m 100m ?170 ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 offset (hz) phase noise (dbc/hz) 16 32 62 1 2 8 4 13 1 10-007 1k 10k 100k 1m 10m 100m ?170 ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 offset (hz) phase noise (dbc/hz) 16 32 62 1 2 8 4 13 1 10-008
HMC832A data sheet rev. b | page 10 of 48 figure 9 . fractional spurio us performance at 904 mhz, exact frequency mode on, 122.88 mhz x tal , pfd = 61.44 mhz, channel spacing = 200 khz, loop filter type 2 (see table 13 ) figure 10 . fractional spurious perform ance at 2118.24 mhz, exact frequency mode on, 122.88 mhz x tal , pfd = 61.44 mhz, channel spacing = 240 khz, loop filter type 2 (see table 13 ) figure 11 . fractional spurious performance at 2646.96 mhz, exact frequency mode on, 122.88 mhz x tal , pfd = 61.44 mhz, channel spacing = 240 khz, loop filter type 2 (see table 13 ) figure 12 . fractional spurious performance at 18 04 mhz, exact frequency mode on, 122.88 mhz x tal , pfd = 61.44 mhz, channel spacing = 200 khz, loop filter type 2 (see table 13 ) figure 13 . fractional spurious performance at 2118.24 mhz , identical configuration to figure 10 with exact frequency mode off figure 14 . fractional spurious performance at 2646.96 mhz, identical configuration to figure 11 with exact frequency mode off ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg 0x03[10] = 1d) ssb integr a ted phase noise = ?64.3dbc integr a tion bandwidth = 1khz t o 100mhz snr = 61.3db, evm = 0.086%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg 0x03[10] = 3d) ssb integr a ted phase noise = ?65.5dbc integr a tion bandwidth = 1khz t o 100mhz snr = 62.5db, evm = 0.075% phase noise integr a tion bandwidth 1khz t o 100mhz 13 1 10-009 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m high performance mode (vco_reg 0x03[10] = 3d) ssb integr a ted phase noise = ?57.45dbc integr a tion bandwidth = 1khz t o 100mhz snr = 54.45db, evm = 0.189%, phase noise integr a tion bandwidth 1khz t o 100mhz low current mode (vco_reg 0x03[10] = 1d) ssb integr a ted phase noise = ?57dbc integr a tion bandwidth = 1khz t o 100mhz snr = 54db, evm = 0.199%, phase noise integr a tion bandwidth 1khz t o 100mhz 13 1 10-010 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg 0x03[10] = 1d) ssb integr a ted phase noise = ?55.6dbc integr a tion bandwidth = 1khz t o 100mhz snr = 52.6db, evm = 0.234%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg 0x03[10] = 3d) ssb integr a ted phase noise = ?56dbc integr a tion bandwidth = 1khz t o 100mhz snr = 53db, evm = 0.224%, phase noise integr a tion bandwidth 1khz t o 100mhz 13 1 10-0 1 1 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg 0x03[10] = 1d) ssb integr a ted phase noise = ?58.7dbc integr a tion bandwidth = 1khz t o 100mhz snr = 55.7db, evm = 0.164%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg 0x03[10] = 3d) ssb integr a ted phase noise = ?59dbc integr a tion bandwidth = 1khz t o 100mhz snr = 56db, evm = 0.158%, phase noise integr a tion bandwidth 1khz t o 100mhz 13 1 10-012 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg 0x03[10] = 1d) ssb integr a ted phase noise = ?57dbc integr a tion bandwidth = 1khz t o 100mhz snr = 54, evm = 0.199%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg 0x03[10] = 3d) ssb integr a ted phase noise = ?57.45dbc integr a tion bandwidth = 1khz t o 100mhz snr = 54.45db, evm = 0.189%, phase noise integr a tion bandwidth 1khz t o 100mhz 13 1 10-013 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg 0x03[10] = 1d) ssb integr a ted phase noise = ?55.6dbc integr a tion bandwidth = 1khz t o 100mhz snr = 52.6db, evm = 0.234%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg 0x03[10] = 3d) ssb integr a ted phase noise = ?56dbc integr a tion bandwidth = 1khz t o 100mhz snr = 53db, evm = 0.224%, phase noise integr a tion bandwidth 1khz t o 100mhz 13 1 10-014
data sheet HMC832A rev. b | page 1 1 of 48 figure 15 . low frequency performance, 100 mhz x tal , pd frequency = 50 mhz, loop filter type 3 (see table 13 ), integer mo de, 50 mhz low - pass filter at the output of HMC832A for the 25 mhz curve only, charge pump set to maximum value figure 16 . typical spurious emissions at 2000.1 mhz, tunable 47. 5 mhz reference, loop filter type 2 (see table 13 and the loop filter and frequency changes section) figure 17 . open - loop phase noise figur e 18 . typical spurious emissions at 2000.1 mhz, 50 mhz fixed reference, 50 mhz pd frequency, integer boundary spur inside the loop filter bandwidth (see the loop filter and frequency changes section) figure 19 . typical spurious vs. offset from 2 ghz, fixed 50 mhz reference vs. tunable 47.5 mhz reference (see the loop filter and frequency changes s ection) figure 20 . open - loop phase noise vs. frequency at various temperatures ?170 ?160 ?150 ?140 ?130 ?120 phase noise (dbc/hz) offset (hz) 100 1k 10k 100k 1m 10m 100m 100mhz output 55.55mhz output 25mhz output 13 1 10-015 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m 13 1 10-016 ?180 ?160 ?140 ?120 ?100 ?80 ?40 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m high performance mode on (vco_reg 0x03[1:0] = 3d) 2854mhz 2453mhz 2013mhz 1587mhz 13 1 10-017 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m 13 1 10-018 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) output frequenc y (khz) 2000.01 2000.1 2001 typica l spurious vs. offset from 2ghz, tunable reference ~47.5mhz typica l spurious vs. offset from 2ghz, fixed reference = 50mhz 13 1 10-019 ?170 ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 1000 100 phase noise (dbc/hz) frequenc y (mhz) 300 3000 30 100khz offset al l modes 1mhz offset al l modes 100mhz offset high performance mode 100mhz offset low current mode ?40c +27c +85c 13 1 10-020
HMC832A data sheet rev. b | page 12 of 48 figure 21 . single sideband (ssb) integrated phase noise, high performance mode, loop filter type 2 (see table 13 ) figure 22 . typical single - ended output power vs. frequency (mid gain setting 6 (vco_reg 0x07[3:0] = 6d )) figure 23 . typical rf output power at 2 ghz (single - ended) vs. temperature figure 24 . figure of merit (fom) figure 25 . typical output power vs. frequency and gain (single - ended) figure 26 . rf output return loss ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ssb integr a ted phase noise (dbc) output frequenc y (mhz) 0.0141 0.0447 0.1410 0.4460 100 1000 0.0045 error vec t or magnitude (evm) (%) +85c +27c ?40c phase noise integr a ted from 10khz t o 20mhz 13 1 10-021 ?15 ?10 ?5 0 5 10 15 output power (dbm) frequenc y (mhz) 100 25 3000 1000 phase noise integr a ted from 10khz t o 20mhz high performance mode (vco_reg 0x03[1:0] = 3d) low current mode (vco_reg 0x03[1:0] = 1d) return loss (vco_reg 0x03[5] = 0) return loss (vco_reg 0x03[5] = 1) 13 1 10-022 ?6 ?4 ?2 0 2 4 6 8 10 0 2 4 6 8 10 output power (dbm) gain setting +85c +27c ?40c 13 1 10-023 ?240 ?230 ?220 ?210 ?200 100 1k 10k 100k 1m normalized phase noise (dbc/hz) offset (hz) fom floor ty p fom vs. offset fom 1/f noise 13 1 10-024 100 25 3000 1000 ?20 ?15 ?10 ?5 0 5 10 15 20 frequenc y (mhz) output power (dbm) gain setting = 1 1 (vco_reg 0x07[3:0] = 1 1d) high perfor mance mode low current mode gain setting = 5 (vco_reg 0x07[3:0] = 5d) gain setting = 0 (vco_reg 0x07[3:0] = 0d) 13 1 10-025 ?30 ?25 ?20 ?15 ?10 ?5 0 output frequenc y (mhz) return loss (db) 100 25 8000 1000 return loss 0 (vco_reg 0x03[5] = 0) return loss 1 (vco_reg 0x03[5] = 1) 13 1 10-026
data sheet HMC832A rev. b | page 13 of 48 figure 27 . frequency settling after frequency change, autocalibration enabled, loop filter bandwidth = 127 khz (type 1, see table 13 ) figure 28 . frequency settling after frequency change, manu al calibration, loop filter bandwidth = 127 khz (type 1 in table 13 ) figure 29 . typical vco sensitivity (k vco ) figure 30 . phase settling after frequency cha nge, autocalibration enabled , loop filter bandwidth = 127 khz (type 1, see table 13 ) figure 31 . phase settling after frequency change, manual calibration figure 32 . typical tuning voltage after calibration (see the loop filter and frequency changes section) 2.2 2.4 2.6 2.8 3.0 3.2 time (s) 0 20 40 60 80 100 120 140 160 frequenc y (ghz) settling time t o <10 phase error 13 1 10-027 time (s) 0 20 40 60 80 100 120 140 160 2.495 2.500 2.505 2.510 frequenc y (ghz) settling time t o <10 phase error n o t e : l o o p f i l t e r b a n d wi d t h = 1 2 7 k h z , l o o p f i l t e r p h a s e m a r gi n = 6 1 . t h i s r e s u l t i s d i r e ct l y a ff e c t e d b y l o o p f i l t e r d e sign . f a s t e r s e t t l i n g t i m e i s p o s s i b l e w i t h wi de r l o o p f i l t e r b a n d wi d t h a n d l o w e r p h a s e m a r gi n . 13 1 10-028 10 20 30 40 50 60 70 80 90 0 0.66 1.30 2.00 3.30 tuning vo lt age (v) k vco (mhz/v) 2.60 1587mhz 2013mhz 2854mhz vco_reg 0x00[5:1] = 15d 2453mhz 13 1 10-029 ?200 ?150 ?100 ?50 0 50 100 150 200 phase error (degrees) time (s) 0 20 40 60 80 100 120 140 160 settling time t o <10 phase error 13 1 10-030 ?200 ?150 ?100 ?50 0 50 100 150 200 phase error (degrees) time (s) 0 20 40 60 80 100 120 140 160 settling time t o <10 phase error note: loo p fil ter bandwidth = 127khz, loo p fil ter phase margin = 61. this resu l t is direct l y affected b y loo p fi l ter design. f aster settling time is possible with wider loo p fil ter bandwidth and lower phase margin. 13 1 10-031 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 calibr a ted a t +85c, measured a t ?40c 1330 1710 1900 2090 2280 2470 2660 2850 3040 1520 tuning vo lt age after calibr a tion (v) vco frequenc y (mhz) calibr a ted a t +27c, measured a t +27c calibr a ted a t ?40c, measured a t +85c calibr a ted a t +85c, measured a t +85c calibr a ted a t ?40c, measured a t ?40c f max f min 13 1 10-032
HMC832A data sheet rev. b | page 14 of 48 figure 33. current consumption in si ngle-ended output configuration, output gain configured in vco_reg 0x07[3:0], differential or single-ended mode programmed in vco_reg 0x03[3:2] figure 34. reference input sensitivity, square wave, measured from a 50 source with a 100 external resistor termination figure 35. mute mode isolat ion, measured at output figure 36. current consumption in differential output configuration, output gain configured in vco_reg 0x07[3:0], differential or single-ended mode programmed in vco_reg 0x03[3:2] figure 37. reference input sensitivity, sinusoidal wave, measured from a 50 source with a 100 external resistor termination 160 170 180 190 200 210 220 230 240 current consumption (ma) output frequency (mhz) f o f o /2 f o /62 500 0 1000 1500 2000 2500 3000 high performance mode (vco_reg 0x03[1:0] = 3d) low current consumption mode (vco_reg 0x03[1:0] = 1d) f o /4 output gain 0db output gain 6db 13110-033 220 222 224 226 228 230 232 14mhz square wave 25mhz square wave 50mhz square wave 100mhz square wave fom (dbc/hz) ?12 ?9 ?6 ?3 0 3 ?15 reference power (dbm) 13110-034 ?110 ?90 ?70 ?50 ?30 ? 10 1000 100 frquency (mhz) isol a tion (db) 3000 mute on (vco_reg 0x03[8:7] = 3d) signalonrf_npinwhenrf_npinoff, rf_p pin on (vco_reg 0x03[3:2] = 1d), mute off (on only during vco calibration vco_reg 0x03[8:7] = 1d) both rf_n and rf_p pins off, (vco_reg 0x03[3:2] = 0d), mute off (on only during vco calibration vco_reg 0x03[8:7] = 1d) 13110-035 180 200 220 240 260 current consumption (ma) output frequency (mhz) f o f o /2 f o /4 f o /62 500 0 10001500200025003000 output gain 0db output gain 6db high performance mode (vco_reg 0x03[1:0] = 3d) low current consumption mode (vco_reg 0x03[1:0] = 1d) 13110-036 200 205 210 215 220 225 230 235 ?20 ?15 ?10 ?5 05 14mhz sinusoidal 25mhz sinusoidal 50mhz square 100mhz square reference power (dbm) fom (dbc/hz) 13110-038
data sheet HMC832A rev. b | page 15 of 48 theory of operation figure 38. pll and vco subsystems the HMC832A pll with integrated vco is composed of two subsystems: pll subsystem and vco subsystem, as shown in figure 38. pll subsystem overview the pll subsystem divides down the vco output to the desired comparison frequency via the n-divider (integer value set in register 0x03, fractional value set in register 0x04), compares the divided vco signal to the divided reference signal (reference divider set in register 0x02) in the phase detector (pd), and drives the vco tuning voltage via the charge pump (cp) (configured in register 0x09) to the vco subsystem. some of the additional pll subsystem functions include ? - configuration (register 0x06). ? exact frequency mode (configured in register 0x0c, register 0x03, and register 0x04). ? lock detect (ld) configuration (use register 0x07 to configure ld and register 0x0f to configure the ld/sdo output pin). ? external cen pin used for the hardware pll enable pin. the cen pin does not affect the vco subsystem. typically, only writes to the divider registers (integer part uses register 0x03, fractional part uses register 0x04) of the pll subsystem are required for HMC832A output frequency changes. the divider registers of the pll subsystem (register 0x03 and register 0x04) set the fundamental frequency (1500 mhz to 3000 mhz) of the vco subsystem. output frequencies ranging from 25 mhz to 1500 mhz are generated by tuning to the appropriate fundamental vco frequency (1500 mhz to 3000 mhz) by programming the n divider (register 0x03 and register 0x04) and programming the output divider (divide by 1 to 62, in vco_reg 0x02) in the vco subsystem. for detailed frequency tuning information and an example, see the frequency tuning section. vco subsystem overview the vco subsystem consists of a capacitor switched step tuned vco and an output stage. in typical operation, the vco subsystem is programmed with the appropriate capacitor switch setting that is executed automatically by the pll subsystem autocalibration state machine when autocalibration is enabled (register 0x0a[11] = 0; see the vco calibration section for more information). the vco tunes to the fundamental frequency (1500 mhz to 3000 mhz), and is locked by the cp output from the pll subsystem. the vco subsystem controls the output stage of the HMC832A , enabling configuration of ? user defined performance settings (see the programmable performance technology section) that are configured via vco_reg 0x03[1:0]. ? vco output divider settings that are configured in vco_reg 0x02 (divide by 2 to 62 to generate frequencies from 25 mhz to 1500 mhz, or divide by 1 to generate fundamental frequencies between 1500 mhz and 3000 mhz). ? output gain settings (vco_reg 0x07[3:0]). ? output return loss setting (vco_reg 0x03[5]). see figure 26 for more information. ? single-ended or differential output operation (vco_reg 0x03[3:2]). ? mute (vco_reg 0x03[8:7]). spi configuration of pll and vco subsystems the two subsystems (pll subsystem and vc o subsystem) have their own register maps as shown in the pll register map and vco subsystem register map sections. typically, writes to both register maps are required for initialization and frequency tuning operations. as shown in figure 38, the pll subsystem is connected directly to the spi of the HMC832A , whereas the vco subsystem is connected indirectly through the pll subsystem to the rf_n rf_p vtune ref buff rf buffer en pll buff pll buff en vspi vspi cal control 4 modulator charge pump phase frequency detectop r divider pll only xrefp cen cp sen sdi sck ld/sdo n divider cal vco en cntrl f o or n or 2 3 13110-043
HMC832A data sheet rev. b | page 16 of 48 HMC832A spi. as a result, writes to the pll register map are written directly and immediately, whereas the writes to the vco subsystem register map are written to the pll register 0x 05 and forwarded via the internal vco spi (vspi) to the vco subsystem. this is a f orm of indirect addressing. vco subsystem registers are write only and cannot be read. for m ore information , see the vco serial port interface (vspi) section. vco serial port interface (vspi) the HMC832A communicates with the internal vco subsystem via an internal 16 - bit vco spi. the internal serial port control s the step tuned vco and other vco subsystem functions. t he internal vspi runs at the rate of t he autocalibration finite state machine ( fsm ) clock, t fsm ( see the vco autocalibration section ) , where the fsm clock frequency cannot be greater than 50 mhz. the vspi clock rate is set by register 0x 0 a[ 14:13 ]. writ es to the control registers of the vco are handled indi - rectly via writes to register 0x 05 of the HMC832A . a write to register 0x 05 causes the internal pll subsystem to forward the packet, msb f irst, across its internal serial link to the vco subsystem, where it is interpreted. vspi use of reg ister 0x 05 the packet data written into register 0x 05 is subparsed by logic at the vco subsystem into the following three fields: field 1 bits[ 2:0] : 3 - bit v co_id, target subsystem address = 000b. field 2 bits [6:3] : 4 - bit vco_reg addr, the internal register address inside the vco subsystem. field 3 bits [15:7] : 9 - bit vco_data, the data field to write to the vco register. for example, to write 0 1111 1110 into r egister 2 of the vco subsystem (vco_id = 000 b), and set the vco output divider to divide by 62, the following must be written to register 0x 05 = 0 1111 1110b , 0010 b , 000 b or , equivalently , register 0x 05 = 0x 7f10 . during autocalibration , the autocalibration controller writes into the vco register address specified by the vco_id and vco_reg addr, as stored in register 0x 05[2:0] and register 0x 05[6:3] , respectively. autocalibration requires that these values be zero ( register 0x 05[6:0] = 0) ; otherwise, when the y are not zero ( register 0x 05[6:0] 0), autocalibration does not f unction. to ensure that the autocalibration functions , it is critical to write register 0x 05[6:0] = 0 after the last vco subsystem write but prior to an output frequency change that is triggered by a write to either register 0x 03 or register 0x 04. however, it is impossible to write only register 0x 05[6:0] = 0 ( vco_id and vco_reg addr ) without writing vco_data ( register 0x 05[15:7]). therefore, to ensure that vco_data ( register 0x 05[15:7]) is not changed , it is required to read the switch settings provided in register 0x 10[7:0], and then rewrite them to register 0x 05 [15:7] , as follows: 1. read register 0x10 . 2. write to register 0x05[15:14] = register 0x10[7:6] ; register 0x05[13] = 1 ( reserved bit ); register 0x05[12:8] = register 0x10 [4:0] ; and register 0x05[7:0] = 0. changing the vco subsystem configuration ( see the vco subsystem register map section ) without following th is procedure result s in a failure to lock to the desired frequency. for a pplications not using the read functionality of the HMC832A spi, in which register 0x 10 cannot be read, it is possible to write register 0x 05 = 0x 0 to set register 0x 05[6:0] = 0, which also sets the vco subband setting equal to zero ( register 0x 05[15:7] = 0) , effectively programming incorrect vco subband settings and causing the HMC832A to lose lock. this procedure is then i mmediately followed by a write to ? register 0x 03, if in i nteger m ode ? register 0x 04, if in fractional mode this write effectively retriggers the autocalibration state machine , forcing the HMC832A to relock w hether in integer or fractional mode . this procedure cause s the HMC832A to lose lock and relock after every vco subsystem change. typical output frequency and lock time is shown in figure 27 and figure 30 , respectively. lock time is typically in the order of 100 s for a phase settling of 10, and is dependent on loop filter design (loop filter band - width and loop filter phase margin).
data sheet HMC832A rev. b | page 17 of 48 vco subsystem figure 39 . pll and vco subsystems figure 40 . simplified step tuned vco the HMC832A contains a vco subsystem that can be configured to operate in ? fundamental freque ncy (fo) mode (1500 mhz to 3000 mhz). ? divide by n mode , where n = 2, 4, 6, 8 58, 60, 62 (25 mhz to 1500 mhz). all modes are vco register programmable , as shown in figure 39 . one loop filter design can be used for the entire frequency of operation of the HMC832A . vco calibration vco autocalibration the HMC832A uses a step tuned type vco. a simplified st ep tuned vco is shown in figure 40 . a step tuned vco is a vco with a digitally selectable capacitor bank allowing the nominal center frequenc y of the vco to be adjusted or stepped by switching i n and out of the vco tank capacitors. m ore than one capacitor can be switched in at a time. a step tuned vco allows the user to center the vco on the required output frequency while keeping the varactor tuning voltage optimized near the midvoltage tuning p oint of the spi (sen, sdi, sck) ld/sdo vco_reg 0x01[0] vco_reg 0x01[3] en en 1, 2, 4, 6, ... 62 vco_reg 0x01[2] vco_reg 0x01[1], en vco_reg 0x00[8:1] vco_reg 0x00[0] loo p fi l ter vco vco ca l volt age en vco_reg 0x07[3:0] vco_reg 0x02[5:0] vco contro l vspi vtune rf_n rf_ p v dd master enable vco subsystem vco_reg 0x03[1:0] vco_reg 0x03[3] vco_reg 0x03[2] vco_reg 0x01[5] vco subsystem performance tuning contro l modul a t or n divider cp phase frequenc y detec t or charge pum p r divider xref p ca l 13 1 10-044 host sck synthesizer sdi cp vco rf out vco subband select vco vspi loo p fi l ter vco input vtune dtune vsck vsdo vsle sen 13 1 10-045
HMC832A data sheet rev. b | page 18 of 48 HMC832A charge pump. this enables the pll charge pump to tune the vco over the full range of operation with both a low tuning voltage and a low tuning sensitivity (k vco ). the vco swi tches are normally controlled automatically by the HMC832A using the autocalibration feature. the autocalibration feature is implemented in the internal state machine. it manages the selection o f the vco subband (capacitor selection) when a new frequency is programmed. the vco switches can also be controlled directly via register 0x 05 for testing or for special purpose operation s . other control bits specific to the vco are also sent via register 0x 05. to use a step tuned vco in a closed loop, the vco must be calibrated such that the HMC832A knows which switch position on the vco is optimum for the desired output frequency. the HMC832A supports autocalibration of the step tuned vco. the autocalibration fixes the vco tuning voltage at the optimum midpoint of the charge pump output, then measures the free running vco frequency wh ile searching for the setting , which results in the free running output frequency that is closest to the desired phase - locked frequency. this procedure results in a phase - locked oscillator that locks over a narrow voltage range on the varactor. a typical t uning curve for a step tuned vco is shown in figure 41 . note that the tuning voltage stays in a narrow range over a wide range of output frequencies. figure 41 . typical vco tuning voltage after calibration the calibration is normally run automatically , once for every change of frequency. this autocalibration ensures optimum selection of vco switch settings vs. time and temperature. the user does not normally need to be concerned about whic h switch setting is used for a given frequency because this is handled by the autocalibration routine. the accuracy required in the calibration affects the amount of time required to tune the vco. the calibration routine searches for the best step setting that locks the vco at the current programmed frequency and ensures that the vco stays locked and perform s well over its full temperature range without additional calibration, regardless of the temperature at which the vco was calibrated. autocalibration c an also be disabled , thereby allowing manual vco tuning. refer to the manual vco calibration for fast frequency hopping section for more information about manual tuning . autocalibration using register 0 x05 autocali bration transfers switch control data to the vco subsystem via register 0x05. the address of the vco subsystem in register 0x05 is not altered by the autocalibration routine. the address and id of the vco subsystem in register 0x05 must be set to the corre ct value before autocalibration is executed. for more information, see the vco serial port interface (vspi) section. automatic relock on lock detect failure it is possible , by setting register 0x07[13] , to have the vco subsys - tem automatically rerun the calibration routine and relock itself if the lock detect indicates an unlocked condition for any reason. with this option, the system attempts to relock only once. vco autocalibration on frequency change assuming reg ister 0x0a[11] = 0, the vco calibration starts automatically whenever a frequency change is requested. to rerun the autocalibration routine for any reason at the same frequency, rewrite the frequency change with the same value, and the autocalibration rout ine executes again without changing the final frequency. vco autocalibration time and accuracy the vco frequency is counted for t mmt , the period of a single autocalibration measurement cycle. t mmt = t xtal r 2 n (1) where: t xtal is the period of the exte rnal reference (crystal) oscillator. r is the reference path division ratio currently in use, set in register 0x02. n is set by register 0x0a[2:0] and results in measurement periods that are multiples of the pd period, t xtal r. the vco autocalibration co unter, on average, expects to register n counts, rounded down (floor) to the nearest integer, for every pd cycle. n is the ratio of the target vco frequency, f vco , to the frequency of the pd, f pd , where n can be any rational number supported by the n divid er. n is set by the integer and fractional register contents using equation 2 . n = n int + n frac /2 24 (2) where: n int is the integer set in register 0 x 03. n frac is the fractional part set in register 0 x 04. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1330 1520 1900 2090 3040 2850 2660 2470 2280 1710 tuning vo lt age after calibr a tion (v) vco frequenc y (mhz) calibr a ted a t +8 5 c, measured a t +8 5 c calibr a ted a t +8 5 c, measured a t ?4 0 c calibr a ted a t ?40c, measured a t ?4 0 c calibr a ted a t ?40c, measured a t +85c calibr a ted a t +27c, measured a t +27c f min f max 13 1 10-046
data sheet HMC832A rev. b | page 19 of 48 the autocalibration state machine and the data tra nsfers to the internal vco vsp i run at the rate of the fsm clock, t fsm , where the fsm clock frequency cannot be greater than 50 mhz. t fsm = t xtal 2 m (3) where m is 0, 2, 4 , or 5 as determined by register 0x 0a[14:13] . the expected number of vco counts, v, is given by v = floor ( n 2 n ) (4) the nominal vco frequency measured, f vcom , is given by f vcom = v f xtal / (2 n r ) (5) where the worst case measurement error, f err , is f err f pd / 2 n + 1 (6) a 5 - bit step tuned vco, for example, nominally requires five measurements for calibration or in the worst case , six measure - ments, and therefore , seven vspi data transfers of 20 clock cycles each. the measurement has a programmable number of wait states, k, of 128 fsm cycles defined by register 0x 0a[7:6] = k. total calibratio n time, worst case, is given by t cal = k 128 t fsm + 6 t pd 2 n + 7 20 t fsm (7) or equivalently t cal = t xtal (6 r 2 n + (140 + ( k 128)) 2 m ) (8) for guaranteed hold of lock, across temperature extremes, the resolution must be better than 1/8 th of the frequency step caused by a vco subband switch change. better resolution settings show no improvement. vco autocalibration example the vco subsystem must satisfy the maximum f pd limited by the two following conditions: n 16 ( f int ), n 20.0 ( f frac ) w here : n = f vco / f pd . f pd 100 mhz. f int is integer mode. f frac is fractional - n mode. the minimum n values changes depending on the operating mode. for example, if the vco subsy stem output frequency is to operate at 2.01 ghz and the crystal frequency is f xtal = 50 mhz, r = 1, and m = 0 (see figure 42 ), then t fsm = 20 ns ( 50 mhz). w hen using autocalibration, the maximum autocali bration f sm clock cannot exceed 50 mhz (see register 0x0a[14:13]). the fsm clock does not affect the accuracy of the measure - ment; it only affects the time to produce the result. this same clock clocks the 16 - bit vco serial port. if the time to change frequencies i s not a concern, the calibration time for maximum accuracy can be set and , therefore, the measurement resolution is of no concern. using an input crystal of 50 mhz (r = 1 and f pd = 50 mhz) , the times and accuracies for calibration using equation 6 and equa tion 8 are listed in table 7 , where minimal tuning time is 1/8 th of the vco band spacing. figure 42 . vco calibration table 7 . autocalibration example with f xtal = 50 mhz, r = 1, m = 0 control value register 0 x 0 a 2:0 n 2 n t mmt (s) t cal (s) f err maximum 0 0 1 0.02 4.92 25 mhz 1 1 2 0.04 5.04 12.5 mhz 2 2 4 0.08 5.28 6.25 mhz 3 3 8 0.16 5.76 3.125 mhz 4 5 32 0.64 8.64 781 khz 5 6 64 1.28 12.48 390 khz 6 7 128 2.56 20.16 95 khz 7 8 256 5.12 35.52 98 khz xref calibr a tion window reg 0x02 st art v vco ctr fsm 50mhz max for fsm + vspi clocks reg 0x0a[14:13] m = [0, 2, 4, 5] reg 0x0a[2:0] n = [0, 1, 2, 3, 5, 6, 7, 8] st op t mmt = t xt al r 2 n t pd 2 n 2 m r 13 1 10-047
HMC832A data sheet rev. b | page 20 of 48 across all vcos, a measurement resolution better than 800 khz produce s correct results. set ting m = 0 and n = 5 provides 781 khz of resolution and adds 8.6 s of autocalibration time to a normal frequency hop. after the autocalibration sets the final switch value, 8.64 s after the frequency change command, the fractional register is loaded, and the loop lock s with a normal tran sient predicted by the loop dynamics. therefore, as shown in this example , autocalibration typically adds about 8.6 s to the normal time to achieve frequency lock. use autocalibration for all but the most extreme frequency hopping requirements. manual vco calibration for fast frequency hopping when switch ing frequencies quickly is needed, it is possible to eliminate the autocalibration time by calibrating the vco in advance and storing the switch number vs . frequency infor - mation in the host , which is acco mplished by initially locking the HMC832A on each desired frequency using autocalibration , then reading and storing the selected vco switch settings. the vco switch settings are available in reg ister 0x 10[7:0] after every autocalibration operation. the host must then program the vco switch settings directly when changing frequencies. manual writes to the vco switches are executed immediately as are writes to the integer and fractional registers when autocalibra - tion is disabled. therefore, frequency changes with manual control and autocalibration disabled requires a minimum of two serial port transfers to the pll, once to set the vco switches and once to set the pll frequency. when autocalibratio n is disabled ( register 0x 0a[11] = 1 ) , the vco update s its registers immediately with the value written via register 0x 05. the vco internal transfer requires 16 vsck clock cycles after the completion of a write to register 0x 05. vsck and the autocalibratio n controller clock are equal to the input reference divided by 0, 4, 16 , or 32 as controlled by register 0x 0a[14:13]. for settling time requirements faster than 1 ms , contact analog devices , inc., a pplications s upport. settling times under 100 s are possi ble but certain conditions on performance do exist. registers required for frequency changes in fractional mode in fractional mode (register 0x06[11] = 1), a large change of frequency may require main serial port writes to one of the three following regist ers : ? t he integer register , register 0x 03 . this write is required only if the integer part changes . ? t he vco spi register, register 0x 05. this write is required only for manual control of vco if register 0x 0a[11] = 1, autocalibration is disabled , or to chang e the vco output divider value ( vco_reg 0x 02) . see figure 39 for more information . ? t he fractional register, register 0x 04. the fractional register write triggers a utocalibration when register 0x 0a[11] = 0, and it i s loaded into the modulator automatically after the a utocalibration runs. if a utocalibration is disabled, register 0x 0a[11] = 1, the fractional frequency change is loaded immediately into the modulator when the register is written with no adjustment to the vco. small steps in frequency in fractional mode, with a utocalibration enabled ( register 0x 0a[11] = 0), usually require only a single write to the fractional register. in a w orst case scenario , three main serial port transfers to the HMC832A may be required to change frequencies in fractional mode. if the frequency step is small and the integer part of the frequency does not change, the integer register is not changed. in all cases, in frac tion al mode, it is necessary to write to the fractional register , register 0x 04, for frequency changes. registers required for frequency changes in integer mode in integer mode (register 0x06[11] = 0), a chan ge of frequency requires main serial port writes to the following registers: ? vco spi register, register 0x 05 . this write is required only for manual control of the vco when register 0x 0a[11] = 1 ( a utocalibration disabled) or when the vco output divider value must change (vco_reg 0x02). ? i nteger register , reg ister 0x 03. i n integer mode, an integer register write triggers a utocalibration when register 0x 0a[11] = 0 and it is loaded into the prescaler automatically after a utocalibration runs. if a utocalibration is disabled, register 0x 0a[11] = 1, the integer freq uency change is loaded into the prescaler immediately when written with no adjustment to the vco. normally , changes to the integer register cause large steps in the vco frequency ; therefore, the vco switch settings must be adjusted. autocalibration enabled is the recommended method for integer mode frequency changes. if a uto - calibration is disabled ( register 0x 0a[11] = 1), a prior knowledge of the correct vco switch setting and the corresponding adjustment to the vco is required before executing the integer frequency change. vco output mute function the HMC832A features an intelligent output mute function with the capability to disable the vco output while maintaining fully functional pll and vco subsystems . the mute function is automatically controlled by the HMC832A and provides a variety of mute control options including ? automatic mut e. this option automatically mutes the outputs duri ng vco calibration during output frequency changes. this mode can be useful in eliminating any out of band emissions during frequency changes, and ensuring that the system emits only the desired frequencies. it is enabled by writing vco_reg 0x 03[8:7] = 1d. ? always mute ( vco_reg 0x 03[ 8:7 ] = 3 d). this mode is used for manual mute control.
data sheet HMC832A rev. b | page 21 of 48 typical isolation when the HMC832A is muted is alw ays better than ?50 db, and is approximately ? 40 db better th an disabling the individual outputs of the HMC832A via vco_reg 0x 03[3:2] , as shown in figure 35 . t he vco subsystem registers are not directly accessible . they are written to the vco subsystem via pll register 0x 05. see figure 39 and the vco serial port interface (vspi) section for more information about the vco subsystem s pi. vco built - i n self test (bist) with autocalibration the frequency limits of the vco can be measured using the bist features of the a utocalibration machine by setting r egister 0x 0a[10] = 1 , which freezes the vco switches in one position. vco switches can then be written manually with the varactor biased at the nominal midrail voltage used for a utocalibration . for example , to measure the vco maximum frequency , use s witch 0, written to the vco subsystem via register 0x 05 = 000000001 0000 vco _ id , where vco _ i d = 000b. when a utocalibration is enabled ( register 0x 0a[11] = 0), and a new frequency is written, a utocalibration r un s . the vco frequency error relative to the command frequency is measured and the results are written to register 0x 11[19:0] , where regist er 0x 11[19] is the sign bit. the result is written in terms of vco count error ( see equation 4). for example , if the expected vco is 2 ghz, the reference is 50 mhz, and n is 6, expect to measure 2000/(50/2 6 ) = 2560 counts. if a difference of ? 5 counts is measured in register 0x 11, it means 2555 counts were actually measured . therefore , the actual fre - quency of the vco is 5/2560 low (negative) , or 1.99609375 ghz . with a 2 ghz vco, 50 mhz reference, and n = 6, one count is approximately 781 khz . pll subsystem charge pump (cp) and phase detector (pd) the p hase detector (pd) has two inputs, one from the reference path divider and one from the rf path divider. when in lock , these two inputs are at the same average frequency and are fixed at a cons tant average phase offset with respect to each other. t he frequency of operation of the pd i s f pd . most formula s related to, for example, step size, - modulation, and timers , are functions of the operating frequency of the pd, f pd . f pd is also referred to as the comparison frequency of the pd. the pd compares the phase of the rf path signal with that of the reference path signal and controls the char ge pump output current as a linear function of the phase difference between the two signals. the output current varies linearly over a full 2 radians ( 360 ) of input phase difference. charge pump a simplified diagram of the charge pump is shown in figure 43. the cp consists of four programmable current sources: two controlling the cp g ain ( u p g ain , register 0x 09[13:7], and d own g ain , register 0x 09[6:0]) and two controlling the cp o ffset, where the magnitude of th e offset is set by register 0x 09[20:14], and the direction is selected by register 0x 09[21] = 1 for up offset and register 0x 09[22] = 1 for down offset. cp g ain is used at all times, wh ereas cp o ffset is recommended for fractional mode of operation only . t ypically , the cp u p and d own gain settings are set to the same value ( register 0x 09[13:7] = register 0x 09[6:0]). charge pump gain charge pump u p and d own gains are set by register 0x 09[13:7] and register 0x09[6:0], respectively. the current gain of the pum p in a mps/radian is equal to the gain setting of this register ( register 0x09 ) divided by 2 . t he t ypical cp gain setting is set from 2 ma to 2.5 ma ; however , lower values can also be used. note that v alues less than 1 ma may result in degraded phase noise performance. for example, if both register 0x 09[13:7] and register 0x 09 [6:0] a re set to 50 decimal, the output current of each pump is 1 ma , and the phase frequency detector ga in is k p = 1 ma/2 radians, or 159 a/rad. see the charge pump (cp) and phase detector (pd) section for more informa tion. figure 43 . charge pump gain and offset control u p pd ref pa th vco pa th loo p fi l ter u p gain reg 0x09[13:7] u p offset reg 0x09[21] 0 a t o 635 a 5 a ste p reg 0x09[20:14] down offset reg 0x09[22] 0 a t o 635 a 5 a ste p reg 0x09[20:14] 0m a t o 2.54m a 20 a ste p 0m a t o 2.54m a 20 a ste p down gain reg 0x09[6:0] dn 13 1 10-048
HMC832A data sheet rev. b | page 22 of 48 charge pump phase offset in integer mode , the phase detector operates with zero offset. the divided reference signal and the divided vco signal arrive at the phase detector inputs at the same time. integer mode does not require any cp o ffset current. when operating in integer mode, disable the cp offset in both directions ( up and down) by writing register 0x 09[22:21] = 00 b , and set the cp o ffset magnitude to zero by writing r egister 0x 09[20:14] = 0 . in fractional mode, cp linearity is o f paramount importance. any non linearity degrades phase noise and spurious perfor - mance. t hese nonlinearities are eliminated by operating the pd with an average phase offset, either positive or negative (either the reference or the vco edge always leads, that is, arrives first at the pd). a programmable cp offset current source add s dc current to the loop filter and create s the desired phase offset. positive current causes the vco to lead, wherea s negative current causes the reference to lead. the c p offset is controlled via register 0x 09. increasing the offset current causes the phase offset to scale from 0 to 360 . the specific level of charge pump offset current ( register 0x 09, bits [20:14] ) is calculated using equation 9 and shown in figure 44. required cp offset = min ( (4.3 10 ?9 f pd i cp ), 0.25 i cp ) (9) where: f pd is the c omparison frequency of the phase dete ctor (hz) . i cp is the full - scale current setting (a) of the switching charge pump (set in register 0x 09[6:0] and register 0x 09[13:7]) . figure 44 . recommended cp offset current vs . phase detector f requency for t ypical cp gain currents, calculated u sing equation 9 do not allow t he required cp offset current to exceed 25 % of the programmed cp current. it is recommended to enable the u p o ffset and disable the down offset by writing register 0x 09 [22:21] = 01b. operation with cp offset influences the required configuration of the lock detect function. see the description of the lock detect function in the lock detect section . phase detector functions register 0x0b, the p hase detector register , allows manual access to control special phase detector features. setting register 0x 0 b[ 5 ] = 0 masks the pd up output, which prevents the charge pump from pumping up. se tting register 0x 0 b[ 6 ] = 0 masks the pd down output, which prevents the charge pump from pumping down. clearing both register 0x 0b[5] and register 0x 0 b[ 6 ] tristates the charge pump while leaving all other functions operating internally. the pd force cp up ( register 0x 0b[9] = 1 ) and f orce cp down ( register 0x 0b[10] = 1 ) bits allow the charge pump to be forced up or down , respectively. this forces the vco to the ends of the tu n ing range, which is useful in testing the vco. reference input stage figure 45 . reference path input stage the reference buffer provides the path from an external refer - ence source (generally crystal - based) to the r divider, and eventually to the phase detector. the buffer has two modes of operation con trolle d by register 0x 08[21]. high g ain ( register 0x 08[21] = 0) is recommended below 200 mhz, and h igh frequency ( register 0x 08[21] = 1) for 200 mhz to 350 mhz operation. the buffer is internally dc biased with 100 internal termination. for a 50 match, add a n ex ternal 100 resistor to ground followed by an ac coupling capacitor (impedance less than 1 ). at low frequencies, a relatively square reference is recommended to maintain a high input slew rate . at higher frequencies, use a square or sinusoid . table 8 shows the recommended operating regions for different reference frequencies. if operating outside these regions , the device usually still operate s , but with degraded reference path phase noise performance. when o perating at 50 mhz, the i nput referred phase noise of the pll is between ? 148 dbc/hz and ? 150 dbc/hz at a 10 khz offset , depending on the mode of operation. to avoid degra - dation of the pll noise contribution, t he input reference signal must be 10 db better than this floor . s uch low levels are only necessary if the pll is the d ominant noise contributor and these levels are required for the system goals. reference path r divider the reference path r divider is based on a 14- bit counter and can divide input signals by values from 1 to 16,383 and is controlled via register 0 x 02. 0 100 200 300 400 500 600 700 0 20 40 60 80 100 recommended offset current (a) phase detec t or frequenc y (mhz) cp current = 2.5m a cp current = 2m a cp current = 1m a 13 1 10-049 xref p 80 v bias 20 ac couple 100 r vdd 13 1 10-050
data sheet HMC832A rev. b | page 23 of 48 rf path, n divider the main rf path divider is capable of average divide ratios between 2 19 ? 5 (524,283) and 20 in fractional mode, and between 2 19 ? 1 (524,287) and 16 in integer mode. the vco frequency range divided by the minimum n divider value places practical restrictions on the maximum usable pd frequency. for example, a vco operating at 1.5 ghz in fractional mode with a minimum n divider value of 20 has a maximum pd frequency of 75 mhz. lock detect the lock detect (ld) function verifies that the HMC832A is generating the desir ed frequency. it is enabled by writing register 0x07[3] = 1. the HMC832A provides an ld indicator in one of two ways. ? as an output available on the ld/sdo pin of the HMC832A (configuration is required to use the ld/sdo pin for ld purposes ; for more information, see the s erial p ort and the configuring th e ld/sdo pin for ld output sections). ? r eading from register 0 x 12[ 1 ], where bit 1 = 1 indicates a locked condition and bit 1 = 0 indicates an unlocked condition. the ld circuit expects the divided vco edge and the divided reference edge to appear at the pd within a user specified time period (window), repeatedly. either signal may arrive first. only the difference in arrival times is significant. the arrival of the two edges within the designated window increments an internal counter. when the count reaches and exceeds a user specified value (register 0x07[2:0]) , the HMC832A declares lock. failure in registering the two edges in any one window resets the counter and immediately declares an unlocked condition. lock is deemed to be reestablished when the counter reaches the user specified value (register 0 x 07[ 2:0 ]) again. the HMC832A supports two lock detect modes. ? analog ld supports a fi xed window size of 10 ns. analog ld mode is selected by writing register 0x07[6] = 0. ? digital ld supports a user configurable window size, programmed in register 0 x 07[ 11:7 ]. digital ld is selected by writing register 0 x 07[ 6 ] = 1 . lock detect configuration optimal spectral performance in fractional mode requires cp current and cp offset current configuration, described in detail in the charge pump (cp) and phase detector (pd) section. the settings in register 0x09 im pact the required ld window size in fractional mode of operation. to function, the required lock detect window size is provided by equation 10 in fractional mode and equation 11 in integer mode. ld window (sec) = 2 ) hz ( 1 (sec) 10 66 . 2 (a) (hz) (a) 9 _ ? ? ? ? ? ? ? ? + + ? pd cp pd offset cp f i f i (10) pd f window ld = 2 1 (sec) (11) where: f pd is the comparison frequency of the phase detector. i cp_offset is the charge pump offset current (register 0 x 09 [ 20:14 ]). i cp is the full - scale current setting of the switching charge pump (register 0 x 09[ 6:0 ] or register 0 x 09[ 13:7 ]). if the result provided by equation 10 is equal to 10 ns, analog ld can be used (register 0x07[6] = 0); otherwise, digital ld is necessary (register 0x07[6] = 1). table 9 lists the required register 0x07 settings to appropriately program the digital ld window size. from table 9 , select the closest value in the digital ld window size columns to the ones calculated in equation 10 and equation 11, and program register 0x07[11:10 ] and register 0 x 07[ 9:7 ] accordingly. table 8 . reference sensitivity 1 reference input frequency (mhz) square input sinusoidal input slew 0.5 v/ns recommended swing (v p - p ) recommended power range (dbm) recommended min imum max imum recommended min imum max imum < 10 yes 0.6 2.5 no no no 10 y es 0.6 2.5 no no no 25 y es 0.6 2.5 okay 8 15 50 y es 0.6 2.5 y es 6 15 100 y es 0.6 2.5 y es 5 15 150 okay 0.9 2.5 y es 4 12 200 okay 1.2 2.5 y es 3 8 1 okay means the setting works. for example, 150 mhz input square wave is sufficient but 100 mhz may provide improved performan ce.
HMC832A data sheet rev. b | page 24 of 48 digital window configuration ex ample for this example, assume the device is in fractional mode, with a 50 mhz pd and the following conditions: ? charge pump gain of 2 ma (register 0 x 09[ 13:7 ] = 0 x 64, register 0 x 09[ 6:0 ] = 0 x 64), ? up offset (register 0 x 09[ 22:21 ] = 01b) ? offset current magnitud e of 400 a (register 0 x 09[ 20:14 ] = 0 x 50) apply equation 10 to calculate the required ld window size. ld window (sec) = ns 33 . 13 2 ) hz ( 10 50 1 (sec) 10 66 . 2 ) a ( 10 2 ) hz ( 10 50 ) a ( 10 4 . 0 6 9 3 6 3 = ? ? ? ? ? ? ? ? + + ? ? ? configuring th e ld/sdo pin for ld output setting register 0x0f[7] = 1 and register 0x0f[4:0] = 1 displays the lock detect flag on the ld/sdo pin of the HMC832A . when locked, ld/sdo is high. as the name sugges ts, the ld/sdo pin is multiplexed between the ld and the serial data output (sdo) signals. therefore, ld is available on the ld/sdo pin at all times except when a serial port read is requested, in which case the pin reverts temporarily to the serial data o utput pin, and returns to the lock detect flag after the read is completed. ld can be made available on the ld/sdo pin at all times by writing register 0x0f[6] = 1. in that case, the HMC832A doe s not provide any readback functionality because the sdo signal is not available. cycle slip prevention (csp) when changing the vco frequency and the vco is not yet locked to the reference, the instantaneous frequencies of the two pd inputs are different, and the phase difference of the t wo inputs at the pd varies rapidly over a range much greater than 2 radians. because the gain of the pd varies linearly with phase up to 2 , the gain of a conventional pd cycles from high gain, when the phase difference approaches a multiple of 2, to l ow gain, when the phase difference is slightly larger than a multiple of 0 radians. the output current from the charge pump cycles from maximum to minimum, even though the vco has not yet reached its final frequency. the charge on the loop filter small cap acitor may actually discharge slightly during the low gain portion of the cycle. this discharge can make the vco frequency reverse temporarily during locking. this phenomenon is known as cycle slipping. cycle slipping causes the pull - in rate during the loc king phase to vary cyclically. cycle slipping increases the time to lock to a value greater than that predicted by normal small signal laplace transform analysis. the HMC832A pd features an abil ity to reduce cycle slipping during acquisition. the cycle slip prevention (csp) feature increases the pd gain during large phase errors. the specific phase error that triggers the momentary increase in pd gain is set via register 0 x 0 b[ 8:7 ]. frequency tuni ng the HMC832A vco subsystem always operates in the fundamental frequency of operation (1500 mhz to 3000 mhz). the HMC832A generates frequencies below its fundamental frequency (25 mhz t o 1500 mhz) by tuning to the appropriate fundamental frequency and selecting the appropriate output divider setting (divide by 2 to 62 ) in vco_reg 0 x 02[ 5:0 ]. the HMC832A automatically controls frequency tuning in the fundamental band of operation . f or more information , see the vco autocalibration section. to tune to frequencies below the fundamental fr equency range (<1500 mhz), it is required to tune the HMC832A to the appropri - ate fundamental frequency, and then select the appropriate output divider setting (divide by 2 to 62) in vco_reg 0x0 2 [ 5:0 ]. table 9 . typical digital lock detect window ld timer speed, register 0x0711:10 digital lock detect window size nominal value (ns) ld timer divide setting , register 0x07 9:7 000 001 010 011 100 101 110 111 00 (faste st) 6.5 8 11 17 29 53 100 195 01 7 8.9 12.8 21 36 68 130 255 10 7.1 9.2 13.3 22 38 72 138 272 11 slowest 7.6 10.2 15. 4 26 47 88 172 338
data sheet HMC832A rev. b | page 25 of 48 integer mode the HMC832A is capable of operating in integer mode. for integer mode, set the following registers: ? disable the fractional modulator, register 0x06[11] = 0 ? bypass the modulator circuit, register 0x06[7] = 1 in integer mode, the vco step size is fixed to that of the pd frequency. integer mode typically has a 3 db lower phase noise than fractional mode for a given pd operating frequency. integer mode, however, often requires a lower pd frequency to meet step size requirements. the fractional mode advantage is that higher pd frequencies can be used; therefore, lower phase noise can often be realized in fractional mode. disable the charge pump offset when in integer mode. integer frequency tuning in integer mode, the digital - modulator is shut off and the n divider (register 0x03) can be programmed to any integer value in the range of 16 to 2 19 ? 1. to run in integer mode, configure register 0x06 (as described in the integer mode section), then program the integer portion of the frequency as explained by equation 12, ignoring the fractional part. 1. disable the fractional modulator, register 0x06[11] = 0. 2. bypass the - modulator register 0x06[7] = 1. 3. to tune to frequencies (<1500 mhz), select the appropriate output divider value vco_reg 0x02[5:0]. writing to the vco subsystem registers (vco_reg 0x02[5:0] and vco_reg 0x03[0] in this case) is accomplished indirectly through pll register 0x05. more information on communi- cating with the vco subsystem through pll register 0x05 is available in the vco serial port interface (vspi) section. fractional mode set the following registers to place the HMC832A in fractional mode: ? enable the fractional modulator, register 0x06[11] = 1. ? connect the - modulator in circuit, register 0x06[7] = 0. fractional frequency tuning this is a generic example with the goal of explaining how to program the output frequency. actual variables are dependent on the reference in use. the HMC832A in fractional mode achieves frequencies at fractional multiples of the reference. the frequency of the HMC832A , f vco , is given by frac int frac int xtal vco ffnn r f f ??? ? ) ( (12) f out = f vco / k (13) where: f out is the output frequency after any potential dividers. k is 1 for fundamental, or k = 2 to 62 depending on the selected output divider value (register 0x05[6:0] indirectly addressed to vco_reg 0x02[5:0]). n int is the integer division ratio (set in register 0x03), an integer number between 20 and 524,284. n frac is the fractional part, from 0.0 to 0.99999, n frac = register 0x04/2 24 . r is the reference path division ratio (set in register 0x02). f xtal is the frequency of the reference oscillator input. for example, f out = 1402.5 mhz, k = 2, f vco = 2805 mhz, f xtal = 50 mhz, r = 1, f pd = 50 mhz, n int = 56, and n frac = 0.1. f pd is the pd operating frequency, f xtal /r. register 0x04 = round(0.1 2 24 ) = round(1,677,721.6) = 1,677,722. errorhz192.1mh2805 2 1677722 56 1 1050 24 6 ? ? ? ? ? ? ? ? ? ? z f vco (14) errorhz596.0mhz5.1402 2 ? ?? vco out f f (15) in this example, the output frequency of 1402.5 mhz is achieved by programming the 19-bit binary value of 56d = 0x38 into the intg_reg bit in register 0x03, and the 24-bit binary value of 1677722d = 0x19999a into the frac bit in register 0x04. elimi- nate the 0.596 hz quantization error using the exact frequency mode, if required. in this example, the output fundamental is divided by 2. specific control of the output divider is required. see the vco subsystem register map section and description for details. exact frequency tuning due to quantization effects, the absolute frequency precision of a fractional pll is normally limited by the number of bits in the fractional modulator. for example, the frequency resolution of a 24-bit fractional modulator is set by the pd comparison rate divided by 2 24 . the 2 24 value in the denominator is sometimes referred to as the modulus. analog devices plls use a fixed modulus, which is a binary number. in some types of fractional plls, the modulus is variable, allowing exact frequency steps to be achieved with decimal step sizes. unfortunately, small steps using small modulus values result in large spurious outputs at multiples of the modulus period (channel step size). for this reason, analog devices plls use a large fixed modulus. normally, the step size is set by the size of the fixed modulus. in the case of a 50 mhz pd rate, a modulus of 2 24 results in a 2.98 hz step resolution, or 0.0596 ppm. in some applications, it is necessary to have exact frequency steps, and even an error of 3 hz cannot be tolerated. fractional plls are able to generate exact frequencies (with zero frequency error) if n can be exactly represented in binary (for example, n = 50.0, 50.5, 50.25, 50.75, ). some common frequencies cannot be exactly represented. for example, n frac = 0.1 = 1/10 must be approximated as round((0.1 2 24 )/2 24 ) 0.100000024. at f pd = 50 mhz, this translates to a 1.2 hz error. the exact frequency mode of the HMC832A addresses this issue and can eliminate quantization error by programming the
HMC832A data sheet rev. b | page 26 of 48 channel step size to f pd /10 in register 0x 0c to 10 (in this example). more generally, this feature can be used whenever the desired frequency, f vco , can be exactly represented on a step plan where there is an integer number of steps ( < 2 14 ) across integer - n bounda ries. mathematically, this situation is satisfied if f vcok mod( f gcd ) = 0 (16) where: f vcok is the channel step frequency. 0 < k < 2 24 ? 1, as shown in figure 46. gcd is the greatest common divisor. ? ? ? ? ? ? = 14 1 2 and ) , ( pd gcd pd vco gcd f f f f gcd f were f pd is the frequency of the phase detector. some fractional plls are able to achieve these exact frequencies by adjust ing (shortening) the length of the phase accumulator (the denominator or the modulus of the - modulator) so that the - modulator phase accumulator repeats at an exact period related to the interval frequency (f vcok ? f vco(k ? 1) ) in figure 46 . consequently, the shortened accumulator results in more frequent repeating patterns and , as a result , often leads to spurious emissions at multiples of the repeating pattern period, or at harmonic frequencies of f vcok ? f v co(k ? 1) . for example, in some applications, these intervals may represent the spacing between radio channels, with the spurious occur ring at multiples of the channel spacing. in comparison, the analog devices method is able to generate exact frequencies between adjacent integer - n boundaries while still using the full 24 - bit phase accumulator modulus, thus achieving exact frequency steps with a high phase detector c omparison rate, which allows analog devices plls to maintain excellent phase noise and spuri ous performance in the exact frequency mode . using exact frequency mode if the constraint in equation 16 is satisfied, the HMC832A is able to generate signals with zero frequency error at the de sired vco frequency. exact frequency mode can be re confi gured for each target frequency or be set up for a fixed f gcd that applies to all channels. configuring exact frequency mode for a particular frequency 1. calculate and program the integer register setti ng. register 0x03 = n int = floor ( f vco / f pd ) where the floor function is the rounding down to the nearest integer. 2. then calculate the integer boundary frequency. f n = n int f pd 3. calculate and program the exact frequency register value. register 0x0c = f pd / f gcd where f gcd = gcd ( f vco , f pd ). 4. calculate and program the fractional register setting. register 0x04 ? ? ? ? ? ? ? ? ? = pd n vcok frac f f f n ) ( 2 ceil 24 where ceil is the ceiling function, that is, round up to the nearest integer. to configure the HMC832A for exact frequency mode at f vco = 2800.2 mhz, where the pd rate (f pd ) = 61.44 mhz, proceed as follows: 1. check equation 16 to confirm that the exact frequency mode for this f vco is possible. ? ? ? ? ? ? = 14 2 ) , ( pd gcd pd vco gcd f f and f f gcd f f gcd = gcd (2800.2 10 6 , 61.44 10 6 ) = 120 10 3 > 14 6 2 10 44 . 61 figure 46 . exact frequency tuning integer bounda r y integer bounda r y f n + 1 ? f n = f pd f n f vco1 f vco2 f vco3 f vco = f vco2 f vco4 f n + 1 f vco 14 f vco 14 ? 1 f vco 14 ? 2 13 1 10-051
data sheet HMC832A rev. b | page 27 of 48 2. calculate n int . n int = register 0x03 = 0x2d d 45 10 44 . 61 10 2 . 2800 floor floor 6 6 1 = = ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? pd vco f f 3 calculate the value for register 0 x 0 c register 0x0c = 00 xc 0 d 3072 20000 10 44 . 61 ) 10 44 . 61 , 10 100 ( 10 44 . 61 ) ), (( 6 6 3 6 1 = = = = ? + gcd f f f gcd f pd vcok vcok pd 4 to program register 0x04, calculate the closest integer - n boundary frequency (f n ) that is less than the desired vco frequency (f vco ): f n = f pd n int . usi ng the current example , f n = f pd n int = 45 61.44 10 6 = 2764.8 mhz then register 0x04 = 938000 x 0 d 9666560 10 44 . 61 ) 10 8 . 2764 10 2 . 2800 ( 2 ceil ) ( 2 ceil 6 6 6 24 24 = = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? pd n vco f f f exact frequency channel mode when multiple , equally spaced, exact frequency channels are needed that fall within the same interval ( that i s, f n f vcok < f n + 1 ) , where f vcok is shown in figure 46 and 1 k 2 14 , it is possible to maintain the same integer - n ( register 0x 03) and exact frequency register ( register 0x 0c) settings and only update the fr actional register ( register 0x 04) setting. the exact frequency channel mode is possible when equation 16 is satisfied for at least two equally spaced adjacent frequency channels, that is, the channel step size. to configure the HMC832A for exact frequency channel mode , initially program the i nteger ( register 0x 03) and the exact frequency ( register 0x 0c) for the smallest f vco frequen cy (f vco1 in figure 46) , as follows: 1. calculate and program the integer register setting regis - ter 0x 03 = n int = floor(f vco1 /f pd ), where f vco1 is shown in figure 46 and corresponds to the minimum channel vco frequency. then , the lower int eger boundary frequency is given by f n = n int f pd . 2. calculate and program the exact frequency register value register 0x 0c = f pd /f gcd , where f gcd = gcd ((f vcok + 1 ? f vcok ), f pd ) = greatest common divisor of the desired equidistant channel spacing (f vcok + 1 ? f vcok ) and the pd frequency , f pd . t o switch between various equally spaced intervals (channels) , only the fractional register ( register 0x 04) must be programme d to the desired vco channel frequency ( f vcok ) , as follows : register 0x 04 = ? ? ? ? ? ? ? ? ? = pd n vcok frac f f f n ) ( 2 ceil 24 where f n = floor( f vco1 / f pd ), and f vco1 , as shown in figure 46, represents the smallest channel vco frequency that is greater than f n . t o configure the HMC832A for the exact frequency mode for equally spaced intervals of 100 khz , where the first channel (channel 1) = f vco1 = 2800.200 mhz and the pd rate (f pd ) = 61.44 mhz, proceed as follows: 1. c heck that the exact frequency mode for f vco1 = 2800.2 mhz (channel 1) and f vco2 = 2800.2 mhz + 100 khz = 2800.3 mhz (channel 2 ) is possible. ? ? ? ? ? ? = ? ? ? ? ? ? = 14 14 1 2 and ) , ( and 2 and ) , ( pd gcd2 pd vco2 gcd2 pd gcd1 pd vco gcd1 f f f f gcd f f f f f gcd f 1 30 2 10 44 1 10 120 10 44 1 10 2 200 14 3 = > = = gcd f gcd1 30 2 10 44 1 10 20 10 44 1 10 3 200 14 3 = > = = gcd f gcd2 2 if eq uation 16 is satisfied for at least two of the equally spaced interval (channel) frequencies , f vco1 , f vco2 , f vco3 , f vcon , as it is in equation 17, the HMC832A exact frequency channel mode is p ossible for all desired channel frequencies, and can be configured as follows: register 0x03 = x2d 0 d 45 10 44 . 61 10 2 . 2800 floor floor 6 6 = = ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? pd vco1 f f register 0x0c = 0xc00 d 3072 20000 10 44 . 61 ) 10 44 . 61 , 10 100 ( 10 44 . 61 ) ), (( 6 6 3 6 1 = = = = ? + gcd f f f gcd f pd vcok vcok pd were f vcok + 1 ? f vcok ) is the desired channel spacing (100 khz in this example).
HMC832A data sheet rev. b | page 28 of 48 3. to program re gister 0x04, the closest integer - n boundary frequency, f n , that is less than the smallest channel vco frequency, f vco1 , must be calculated (f n = floor(f vco1 /f pd )). using the current example: mhz 8 . 2764 10 44 . 61 45 10 44 . 61 10 2 . 2800 floor 6 6 6 = = ? ? ? ? ? ? ? ? = pd n f f ten for cannel 1 register 0x04 = ceil ? ? ? ? ? ? ? ? ? pd n vco1 f f f ) ( 2 24 , where f vco1 = 2800.2 mhz. 938000 x 0 d 9666560 10 44 . 61 ) 10 8 . 2764 10 2 . 2800 ( 2 ceil 6 6 6 24 = = ? ? ? ? ? ? ? ? ? = to change from channel 1 (f vco1 = 2800.2 mhz) to channel 2 (f vco2 = 2800.3 mhz), only register 0x04 needs to be programmed, as long as all of the desired exact frequencies , f vcok ( se e figure 46) , fall between the same integer - n boundaries (f n < f vcok < f n + 1 ). in that case, register 0x04 = on so and , eaab 93 x 0 d 9693867 10 44 . 61 ) 10 8 . 2764 10 3 . 2800 ( 2 ceil 6 6 6 24 = = ? ? ? ? ? ? ? ? ? seed register the start phase of the fractional modulator digital phase accumula tor (dpa) can be set to one of four possible default values via the seed bits , register 0x 06[1:0]. the HMC832A automatically reload s the start phase (seed value) into the dpa every time a new fr actional frequency is selected. certain zero or binary seed values may cause spurious energy correlation at specific frequencies. for most c ases , a random (not zero and not binary) start seed is recommended ( register 0x 06[1:0] = 2 ). soft reset and power - on reset the HMC832A features a hardware power - on reset (por). all chip registers ar e reset to default states a pproximately 250 s after power - up. the pll subsystem spi registers can also be soft reset by an spi write to register 0x 00. note that the soft reset does not clear the spi mode of operation referred to in the s erial p ort section . t he vco subsystem is not affected by the pll soft reset ; the vco subsystem registers can only be reset by removing the power supply. i f external power supplies or regulators have rise times slower than 250 s, write to the spi soft reset b it ( register 0x 00[5] = 1) immediately after power - up, before any other spi activity. this write procedure ensure s starting from a known state. power - down mode t he vco subsystem is not affected by the cen pin or soft reset. therefore, device power - down is a two - step process. 1. p ower down the vco by writing 0 to vco r egister 1 via register 0x 05. 2. p ower - down the pll by pulling the cen pin ( p in 17) low (assuming there are no spi overrides ( register 0x 01[0] = 1)) . pulling the cen pin low disables all analog functi ons and internal clocks. current consumption typically drop s below 10 a in the power - down state. the serial port still respond s to normal communication in power - down mode. it is possible to ignore the cen pin by setting register 0x 01[0] = 0. control of th e power - down mode then comes from the serial port register , register 0x 01 [ 1 ]. it is also possible to leave various blocks turned on when in power - down (see register 0x 01), as listed in table 10. table 10 . bit and block assignments for register 0x01 bit assignment block assignment bit 2 internal bias reference sources bit 3 pd block bit 4 cp block bit 5 reference path buffer bit 6 vco path buffer bit 7 digital i/o test pads to mute the output but leave the pll and vco locked , see the vco output mute function section. general - purpose output (gpo) the pll shares the ld/sdo ( l ock d etect/ serial data output ) pin to perform various functions. although the pin is most commonly used to read back registers from the chip via the spi, it is also capable of exporting a variety of signals and real - time test wave - forms (including lock detect ). it is driven by a tri state cmos driver with ~20 0 r out . it has logic associated with it to dynami - cally select whether the driver is enabled, and to decide which data to export from the chip. in its default configuration, after power - on reset, the output driver is disabled, and drives only during appr opriately addressed spi reads. this configuration allows the HMC832A to share its output with other devices on the same bus. the pin driver is enabled if the chip is addressed ; that is, the las t three bits of the spi cycle = 000 b before the rising edge of sen. if sen rise s before sck has clocked in an invalid (nonzero) chip address, the HMC832A start s to drive the bus. to monitor any of the gpo signals, including lock detect , set register 0x 0f[7] = 1 to keep the sdo driver always on. this setting stops the ldo driver from tri stating and means that the sdo line cannot be shared with other devices. the HMC832A naturally switch es from the gpo data and export s the sdo signal during an spi read. to prevent this automatic data selection and always select the gpo signal, set
data sheet HMC832A rev. b | page 29 of 48 bit 6 of register 0x0f to 1 to p revent a uto mux ing of the l d/ sdo pin . the phase noise performance at this output is poor and uncharacter ized. also, do not toggle the gpo output during normal operation because toggling may degrade the spectral performance. additional controls are available that may be helpful when sharing the bus with other devices . ? to disable the driver completely, set register 0x 08[5] = 0 ( this bit takes precedence over all other ld/sdo driver bit settings ) . ? to disable either the pull - up or pull - down sections of the driver, set register 0x 0f[8] = 1 or register 0x 0f[9] = 1 , respectively. ? to d r ive 3.3 v cmos logic , set register 0x0b[22] = 1 . example s cenarios are listed in table 11. the signals that are available on the gpo are selected by changing the gpo _ select bit, register 0x0f[4:0]. chip identification identify the pll subsystem version information by reading the content of the read only register, chip _id , in register 0x 00 . it is not possible to read the vco subsystem version. s erial p ort interface (spi ) the HMC832A spi supports both 1.8 v and 3.3 v voltage levels. input pins including sdi, sck, and sen support both voltage levels without the need for any configuration. the spi output, the ld/ sdo pin, also supports both 1.8 v and 3.3 v levels in both cmos and ope n - drain configurations. both the voltage levels and configuration (cmos or open drain) are register programmable via register 0x0b[22] and register 0x0f[9:8] , respectively, as shown in table 12. open - drain mode in both 1.8 v and 3.3 v levels requires an external pull - up resistor. see the e lectrical s pecifications in table 1 for more info r mation . spi prot ocol features the spi protocol has the following general features: ? 3 - bit chip address , can addres s up to eight devices connected to the serial bus . ? wide compatibility with multiple protocols from multiple vendors . ? simultaneous w rite/ r ead during the spi cycle . ? 5 - bit address space . ? 3 - wire for w rite o nly capability, 4 - wire for r ead/ w rite capability . typi cal serial po rt operation can be run with sc k at speeds of up to 50 mhz. serial port write operation spi write specifications are listed in table 2 in the spi write timing characteristics section and a typical write cycle is shown in figure 47. the spi write operation is as follows: 1. the master (host) places 24 - bit data, d [ 23:0 ] , msb first, on sdi on t he first 24 falling edges of sc k . 2. the slave ( HMC832A ) shifts in data on sdi on the first 24 rising edges of sc k. 3. the master places a 5 - bit register address to be written to, r [ 4:0 ] , msb first, on the next five falling edges of sck (25 th to 29 th falling edges) . 4. the slave shifts the register bits on t he next five rising edges of sc k (25 th to 29 th rising edges). 5. the master places a 3 - bit chip address, a [ 2:0 ] , msb first, on the next three falling edges of sck (30 th to 32 nd falling edges). analog devices reserves chip address a2 to chip address a0 = 000 for all rf pll s with integrated vcos. 6. the slave shifts the chip address bits on th e next three rising edges of sc k (30 th to 32 nd rising edges). 7. the master asserts sen after the 32 nd ri sing edge of sc k. 8. the slave registers the sdi data on the rising edge of sen. table 11 . driver scenarios scenario action drive sdo during reads, tristate otherwise (allow bus sharing), 1.8 v output none required drive sdo durin g reads, lock detect otherwise, 1.8 v output set gpo select, register 0x0f[4:0] = 00001 b (default) set register 0 x 0 f[ 7 ] = 1 , prevent gpo driver disable always drive lock detect, 3.3 v output set register 0 x 0 f[ 6 ] = 1 , prevent automux of sdo set the gpo select, register 0 x 0 f[ 4:0 ] = 00001 (default) set register 0 x 0 f[ 7 ] = 1 , prevent gpo driver disable set register 0 x 0 b[ 22 ] = 1 , output drive set to 3.3 v logic table 12 . spi voltage register 0 x 0 b[ 22 ] spi voltage level register 0 x 0 f[ 8 ] internal pull - up disable register 0 x 0 f[ 9 ] internal pull - down disable ld/sdo pin configuration dont care dont care dont care ld/sdo pin tristated 1 1 0 3.3 v open - drain mode 0 1 0 1.8 v open - drain mode 1 0 0 3.3 v cmos mode 0 0 0 1.8 v cmos mode
HMC832A data sheet rev. b | page 30 of 48 figure 47 . serial port write timing diagram serial port r ead operation in general, the ld/sdo line is always active during the write cycle. during any spi cycle , ld/sdo contain s the data from the current address writt en in reg ister 0x 0 0[4:0]. if reg ister 0x 0 0[4:0] is not changed , the same data is always present on ld/sdo during a spi cycle . if a read is required from a specific address, it is necessary to write the required address to register 0x 0 0[4:0] in the first spi cycle . then, in the next spi cycle , the desired data becomes available on ld/sdo . a typical read cycle is shown in figure 48 . an example of the two - cycle procedure to read from any random address is as follows : 1. the m aster (host), on the first 24 falling edges of sck , places 24 - bit data, d [ 23:0 ] , msb f irst, on sdi , as shown in figure 48. set d [ 23:5 ] to zero. d [ 4:0 ] = address of the register to be read on the next cycle. 2. t he slave ( HMC832A ) shifts in data on sdi on the first 24 rising edges of sck . 3. the m aster places the 5 - bit register address , r [ 4:0 ] (the read address register), msb first, on the next five falli ng edges of sck (25 th to 29 th falling edges ). r [ 4:0 ] = 00000. 4. the s lave shifts the register bits on the next five rising edges of sck (25 th to 29 th rising edges ). 5. the m aster places the 3 - bit chip address, a [ 2:0 ] , msb first, on the next three falling edges of sck (30 th to 3 2 nd falling edges ). the c hip address is always 000 b. 6. the s lave shifts the chip address bits on the next three rising edges of sck (30 th to 32 nd rising edges ). 7. the master asserts sen after the 32 nd rising edge of sck. 8. the slave registers th e sdi data on the rising edge of sen. 9. the master clears sen to complete the address transfer of the two - part read cycle. 10. if a write data to the chip is not needed at the same time as the second cycle occurs , it is recommended to simply rewrite the same con tents on sdi to register 0x00 on the read back p ortion of the cycle. 11. the master places the same sdi data as the previous cycle on the next 32 falling edges of sck. 12. the slave ( HMC832A ) shifts the sdi data on the next 32 rising edges of sck. 13. the s lave places the desired read data ( that is, data from the address specified in register 0x 00[ 4 :0 ] of the first cycle) on ld/sdo , which automatically switches to sdo mode from ld mode, disabling the ld outpu t. 14. the master asserts sen after the 32 nd rising edge of sck to complete the cycle and to revert back to lock detect on ld/sdo . 1 t 1 t 2 t 5 t 6 t 3 t 4 2 3 22 23 24 25 26 x x d23 d22 d2 d1 d0 a2 a1 a0 r4 r3 r0 30 31 32 sck sdi sen 13 1 10-052
data sheet HMC832A rev. b | page 31 of 48 figure 48 . serial port read timing diagram 1 t 1 t 5 t 4 t 7 t 6 t 2 18 19 20 read address register address = 00000 first cycle chi p address = 000 24 25 29 30 31 32 r0 r3 d0 d4 d5 x x x ld/gpo sck sdi sen ld/sdo or tris ta te ld/gpo x x x x x x x x x x r4 a2 a1 a0 t 3 1 t 1 t 7 t 6 18 19 20 second cycle 24 25 29 30 31 32 r0 r3 d0 d4 d5 d23 x x d23 ld/gpo sck sdi sen ld/sdo ld/gpo 1 1 f o r mor e i n f o r m a t i o n o n u s i n g t h e g p o f u n c t i o n s e e t h e s e r i a l p o r t i n t e r f a c e s e c t i o n . d22 d2 d1 d0 r4 r0 a2 a1 a0 r4 a2 a1 a0 t 3 13 1 10-053
HMC832A data sheet rev. b | page 32 of 48 applications information a large bandwidth (25 mhz to 3000 mhz), industry leading phase noise and spurious performance, excellent noise floor (?160 dbc/hz), and a high level of integration make the HMC832A ideal for a variety of applications, including as an rf or if stage local oscillator (lo). using the HMC832A with a tunable reference, as shown in figure 51, it is possible to drastically improve spurious emissions performance across all frequencies. figure 49. HMC832A in a typical transmit chain figure 50. HMC832A in a typical receive chain figure 51. HMC832A used as a tunable reference for HMC832A hmc1044lp3e hmc900lp5e hmc795lp5e HMC832A pll 2 dac dac HMC832A pll 13110-040 hmc1044lp3e HMC832A HMC832A hmc900lp5e cmio cmqo hmc960lp4e 90 0 pll pll hmcad1520 adc hmcad1520 adc 13110-041 HMC832A crystal oscillator pll HMC832A tunable reference 25mhz to 100mhz pll 13110-042
data sheet HMC832A rev. b | page 33 of 48 power supply the HMC832A is a high performance , low noise device. in some cases , phase noise and spurious performance may be degraded by noisy power supp lies. to achieve maximum performance and ensure that power supply noise does not degrade the per formance of the HMC832A , use the analog devices low noise , high power supply rejection ratio ( psr r) regulator, the hmc1060lp3e . using the hmc1060lp3e lowers the design risk and cost, and ensures that the performance shown in the typical performance characteristics section can be achieved. programmable perform ance technology for low power applications that do not require maximum noise floor performance, the HMC832A features the ability to reduce current consumption by 50 ma (power consumption by 165 mw) at the cost of decreasing phase noise floor performance by ~5 db. high performance is enabled by writing vco_reg 0x 03[1:0] = 3d, an d it is disabled ( low current consumption mode enabled) by writing vco_reg 0x 03[1:0] = 1d. high performance mode improves noise floor performance at the cost of increased current consumption. the r esulting current consumption is shown in figure 33 and figure 36. loop filter and frequency change s figure 52 . loop filter design all plls with integrated vcos exhibit integer boundary spurs at harmonic s of the reference frequency. figur e 18 shows the worst case spurious scenario where the harmonic of the reference frequency (50 mhz) is within the loop filter bandwidth of the fundamental frequency of the HMC832A . the tunable reference changes the reference frequency from 50 mhz in figur e 18 to 47.5 mhz in figure 16 to d istance the harmonic of the reference frequency (spurious emissions) from the fundamental output frequency of the HMC832A so that it is filtered by the loop filter. the internal HMC832A setup and divide ratios are changed in the opposite direction accordingly so that the HMC832A generates an identical output frequency , as sh own in figur e 18 , without the spurious emissions inside the loop bandwidth. using these same procedures, figure 19 is generated by o bserving and plotting only the magnitude of the largest s pur, at any offset and at each output frequency, while using a fixed 50 mhz reference and a tunable 47.5 mhz reference. the HMC832A features an internal a utocalibration process that seamlessly calibrates the HMC832A when a frequency change is executed (see figure 27 and figure 30 ) . t he t ypical frequency settling time that can be expected after any frequency change ( writes to reg ister 0x 03 or reg ister 0x 04 ) is shown in figure 27 with a utocalibration enabled (register 0x 0a[11] = 0). a f re - quency h op of 5 mhz is shown in figure 27; however the settling time is independent of the size of the frequency change. any size frequency hop has a similar settling time with a uto calibration enabled. figure 32 shows the typical tuning voltage after calibration where , when the HMC832A is calibrated at any temperature, the calibration setting holds across the entire opera ting range of the HMC832A (?40c to +85c) . figure 32 shows that the tuning voltage is maintained within a narrow operating range for worst case scenari os where calibration is executed at one temperature extreme and the device is operating at the other extreme. for applications that require fast frequency changes, the HMC832A supports manual c alibration that enables faster settling times (see figure 28 and figure 31) . manual calibrati on must be executed only once for each individual HMC832A device , at any tempera ture, and is valid across all temperature operating range s of the hmc8 32a . for m ore information about manual calibration , see the manual vco calibration for fast frequency hopping section. a f requency hop of 5 mhz is shown in figure 28 and figure 31; however , the settling time is independent of the size of the frequency change. any size frequency hop has a similar settling ti me with a utocalibration disabled (reg ister 0x 0a[11] = 1). table 13 . loop filter designs used in typical performance characteristics graphs loop filter type loop filter bandwidth (khz) loop filter phase margin c 1 (pf) c 2 (nf) c 3 (pf) c 4 (pf) r 2 () r 3 () r 4 () loop filter design type 1 1 127 61 390 10 82 82 750 300 300 see figure 52 type 2 2 75 61 270 27 200 390 430 390 390 see figure 52 type 3 3 214 71 56 1.8 n / a 4 n / a 4 2200 0 0 see figure 52 1 loop filter type 1 is for best integrated phase noise. the loop filter bandwidth is designed for 50 mhz pd frequency, cp = 1 .6 ma at 2.2 ghz output in fractional mode. 2 loop filter type 2 is suggested for best far out phase noise. the loop filter bandwidth is designed for 50 mhz pd frequency, cp = 1.6 ma at 2.2 ghz output in fractional mode. 3 loop filter type 3 is suggested f or best integrated phase noise in integer mode. the loop filter bandwidth is designed for 50 mhz pd frequency, cp = 2.5 ma at 3 ghz output in integer mode. 4 n/a means not applicable. cp vtune c4 c3 c1 c2 r2 r3 r4 13 1 10-037
HMC832A data sheet rev. b | page 34 of 48 rf programmable outp ut return loss the HMC832A features a p rogrammable rf output return loss (vco_reg 0x 03[5]) and 0 db to 1 1 db of programmable gain (vco_reg 0x 07[3:0]) , as shown in figure 26 and figure 25, respectively . maximum o utput power is achieved with a high return loss set ting (vco_reg 0x 03[5] = 0) , as shown in figure 22 . setting vco_reg 0x 03[5] = 1 improves return loss for applica - tions that require it at the cost of reduced rf out put power ( see figure 22 ). mute mode t he HMC832A features a configurable mute mode, as well as the ability to independently turn off outputs on both th e rf_n and rf_p output pins. figure 35 shows isolation measured at the output when the mute mode is on (vco_reg 0x 03[8:7] = 3d), and when the mute mode is off (vco_reg 0x 03[8:7] = 1d) , with either or both outputs d isabled (vco_reg 0x 03[3:2] = 0 d ) or one output enabled and the other disabled (vco_reg 0x 03 [ 3:2 ] = 1 d).
data sheet HMC832A rev. b | page 35 of 48 pll register map id, read address, an d reset ( rst ) registers the id register is read only, the read address/rst strobe register is write only, and the rst register is read/write. table 14. register 0 x 00, id register (read only) bit s type name width default description 23:0 r chip_id 24 j7275 HMC832A chip id tabl e 15. register 0x 00, read address/rst strobe register (write only) bit s type name width default 1 description 4:0 w read a ddress 5 n/a read a ddress for next cycle . this is a write only register. 5 w soft r eset 1 n/a soft r eset for both spi modes (set to 0 for proper operation) . 23:6 w not d efined 18 n/a not d efined (set to 0 for proper operation) . 1 n/a means not applicable. table 16. register 0x 01, rst register (default 0x000002 ) bit s type name width def ault description 0 r/w rst_chipen_pin_select 1 0 1 = power down the pll via the cen pin ( see the power - down mode section ) 0 = power down the pll via the spi (rst_chipen_from_spi) , register 0 x 01 [ 1 ] 1 r/w rs t_chipen_from_spi 1 1 pll enable bit of the spi 9:2 r/w reserved 8 0 reserved reference divider (refdiv) , integer , and fractional frequency registers table 17. register 0x 02, refdiv register (default 0x 000001) bit s type name widt h default description 13:0 r/w rdiv 14 1 reference d ivider r v alue (see e quation 12) . using the d ivider requires the reference path buffer to be enabled ( reg ister 0x 08[3] = 1 ) . 1d rdiv 16,383d. table 18. register 0x 03, frequency register , integer part (default 0x 000019) bit s type name width default description 18:0 r/w intg_reg 19 25d integer divider register. these bits are the vco divider integer part, used in all modes ( see equation 12 ) . fractional m ode . m ax imum 2 19 ? 4 = 0x 7fffc = 524,284d . integer m ode . m in imum 16d . m ax imum 2 19 ? 1 = 0x 7ffff = 524,287d . table 19. register 0x 04, frequency re gister , fractional part (default 0x 000000) bit s type name width default description 23:0 r/w frac 24 0 vco divider fractiona l part (24 - bit unsigned) ; see the fractional frequency tuning section. these bits are u se d in fractional mode only (n frac = register 0x 04/2 24 ). m in imum = 0d ; m ax imum = 2 24 ? 1 .
HMC832A data sheet rev. b | page 36 of 48 vco spi register register 0 x 05 is a special register used for indirect addressing of the vco subsystem. writes to register 0 x 05 are automatically forwarded to the vco subsystem by the vco spi state machine controller. register 0x05 is a read/ write register. however, register 0x05 holds only the contents of the last transfer to the vco subsystem. therefore, it is not possible to read the full contents of the vco subsystem. only the content of the last transfer to the vco subsystem can be read. f or autocalibration , regi ster 0x05 [6:0] must be set to 0. table 20. register 0x 05, vco spi register (default 0x 000000) bit s type name width default description 2:0 r/w vco_id 3 0 internal vco s ubsystem id . 6:3 r/w vco_regaddr 4 0 vco subsystem register address. these bits are f or interfacing with the vco . s ee the vco serial port interface (vspi) section . 15:7 r/w vco_data 9 0 vco s ubsystem data. these bits are used to write the d ata t o th e vco s ubsystem. - configuration register table 21. register 0x 06, - configuration register (default 0x 200b4a) bit type name width default description 1:0 r/w seed 2 2 selects the s eed in f ractional m ode . writes to this register are stored in t he HMC832A and are loaded into the modulator only when a frequency change is executed and when register 0x06[8] = 1. 0 : 0 seed . 1: lsb seed . 2 : 0xb29d08 seed . 3: 0x50f 1cd seed . 6:2 r/w reserved 5 18d reserved . 7 r/w frac_bypass 1 0 bypass fractional mode. in the bypass fractional modulator , the output is ignored, but fractional modulator continues to be clocked when sd enable = 1 . use t his bit to test the isolation of the digital fractional modulator from the vco output in integer mode . 0 : use modulator, required for fractional mode 1 : bypass modulator, required for integer mode. 10:8 r/w initialization 3 3 d program to 7d . 11 r/w sd enable this bit cont rols whether autocalibration starts on an integer or a fractional write. 1 1 0: disable s fractional core, use for integer mode or integer mode with csp . 1: enables fractional core ( required for fractional mode ) , or integer isolation testing. 20 :12 r/w reserved 9 0 reserved . 21 r/w auto matic clock configuration 1 1 program to 0 . 22 r/w reserved 1 0 reserved .
data sheet HMC832A rev. b | page 37 of 48 lock detect register table 22. register 0x 07, lock detect register (default 0x 00014d) bit type name width defau lt description 2:0 r/w lkd_wincnt_max 3 5 d the l ock detect window sets the number of consecutive counts of the divided vco that must be within the lock detect windo w to declare lock 0 : 5 1 : 32 2 : 96 3 : 256 4 : 512 5 : 2048 6 : 8192 7 : 65,535 3 r/w enable internal lock detect 1 1 see the s erial p ort section 5:4 r/w reserved 2 0 reserved 6 r/w lock detect window type 1 1 lock detection window timer selection 1 : digital programmable timer 0 : analog one shot, nominal 10 ns window 9:7 r/w ld digital window duration 3 2 lock detection, digital window duration 0 : half cycle 1 : one cycle 2 : two cycles 3 : four cycles 4: eight cy cles 5 : 16 cycles 6 : 32 cycles 7 : 64 cycles 11:10 r/w ld digital timer frequency control 2 0 lock detect digital timer frequency control ( s ee the lock detect section for more information ) 0 0: fastest 11: slowest 12 r/w reserved 31 0 reserved 13 r/w auto matic r elock : one try 1 0 1: a ttempts to relock if the lock detect fails for any reason ; t ries on e time only analog enable (en) r egister table 23. register 0x 08, analog en register (default 0x c1beff) bit type name width default description 0 r/w bias_en 1 1 enables main chip bias reference 1 r/w cp_en 1 1 charge pump enable 2 r/w pd_en 1 1 pd enable 3 r/w refbuf_en 1 1 reference path buffer enable 4 r/w vc obuf_en 1 1 vco path rf buffer enable 5 r/w gpo_pad_en 1 1 0 : disables the ld / sdo pin 1: enables the g po port or allows a shared spi when bit 5 = 1 and register 0xf[7] = 1, the ld/sdo pin is always driven, which is re quired for use of the gpo port when bit 5 = 1 and register 0xf[7] = 0, sdo is off when an unmatched chip address is seen on the spi, allowing a shared spi with other compatible devices 9:6 r/w reserved 4 11d reserved
HMC832A data sheet rev. b | page 38 of 48 bit type name width default description 10 r/w vco buffer and prescaler bias enable 1 1 vco b uffe r and prescaler bias enable 20:11 r/w reserved 1 55d reserved 21 r/w high frequency reference 1 0 program to 1 for 200 mhz to 350 mhz operation ; p rogram to 0 for <200 mhz 23:22 r/w reserved 2 3 d reserved charge pump register table 24. register 0x 09, charge pump register (default 0x 403264) bit type name width default description 6:0 r/w cp down g ain 7 100d , 0x 64 charge p ump down gain control, 20 a per step . a ffects fractional phase noise and lock detect settings . 0d = 0 a . 1d = 20 a . 2d = 40 a . 127d = 2.54 ma . 13:7 r/w cp up g ain 7 100d , 0x 64 charge pump up gain control, 20 a per step . affects fractional phase noise and lock detect settings . 0d = 0 a . 1d = 20 a . 2d = 40 a . 127d = 2.54 ma . 20:14 r/w offset magnitude 7 0 charge pump offset control, 5 a per step. affects fractional phase noise and lock detect settings. 0d = 0 a . 1d = 5 a . 2d = 10 a . 127d = 635 a . 21 r/w offset up enable 1 0 recommended setting = 1 in fractional mode, 0 otherwise. 22 r/w offset down enable 1 1 recommended setting = 0 . 23 r/w reserved 1 0 reserved. autocalibration regi ster table 25. register 0x 0a , vco autocalibra tion configuration register (default 0x 002205) bit type name width default description 2:0 r/w v tune r esolution 3 5 r divider cycles 0 : 1 cycle 1 : 2 cycles 2 : 4 cycles 7 : 256 cycles 9:3 r/w reserved 7 64d program 8 d 10 r/ w force c urve 1 0 program 0 11 r/w autocalibration d isable 1 0 program 0 for normal operation using vco auto calibration 12 r/w no vspi t rigger 1 0 0: normal operation 1: this bit disables the serial transfers to the vc o subsystem (via register 0x05)
data sheet HMC832A rev. b | page 39 of 48 bit type name width default description 14:13 r/w fsm/vspi clock select 2 1 these bits set the a utocalibration fsm and vspi c lock ( 50 mhz maximum) 0: input crystal reference 1: input crystal reference divide by 4 2: input crystal reference divi de by 16 3: input crystal reference divide by 32 16:15 r/w reserved 2 0 reserved phase de tector (pd) register table 26. register 0x 0b , pd register (default 0x 0f8061) bit type name width default description 2:0 r/w pd_ del_ sel 3 1 sets the pd reset path delay ( r ecommended setting is 001) . 4:3 r/w reserved 2 0 reserved . 5 r/w pd_ up_en 1 1 enables the pd up output . 6 r/w pd_ dn_en 1 1 enables the pd down output . 8:7 r/w csp m ode 2 0 cycle s lip prevention mode. this delay va ries by 10% with temperature and 12% with process. extra current is driven into the loop filter when the phase error is larger than the following: 0 = disabled . 1 = 5.4 ns . 2 = 14.4 ns . 3 = 24.1 ns . 9 r/w force cp up 1 0 force s cp up output to turn on ; u se for t est only . 10 r/w force cp down 1 0 forces cp down output to turn on; use for test only. 21:11 r/w reserved 13 496 d ( 0x1f0 ) reserved. 22 r/w spi voltage level 1 0 ld/sdo pin voltage drive level. 0: 1.8 v spi m ode . 1: 3.3 v spi m ode . 23 r/w reserved 1 0 reserved. exact frequency mode register table 27. register 0x 0c , exact frequency mode register (default 0x 000000) bit type name width default description 13:0 r/w number of channels per f pd 14 0 the c omparison f requency divided by the correction rate m ust be an integer. frequencies at exactly the correction rate have zero frequency error. 0: disabled. 1: disabled . 2:16383d (0x3fff) .
HMC832A data sheet rev. b | page 40 of 48 general - purpose, spi , and re ference divider (gpo _spi_rdiv) register table 28. register 0x 0f , gpo_spi_rdiv register (default 0x 000001) bit type name width default description 4:0 r/w gpo_select 5 1 d the s ignal selected by this bit is an output to the ld/ sdo p in when the ld/ sdo pin is enable via register 0x08[5] 0: d ata from reg ister 0x 0f[5] 1 : lock detect output 2 : lock detect trigger 3 : lock detect window output 4 : ring oscillator test 5: pull - up resistor is ~230 from csp 6: pull - down resistor is ~230 from csp 7 : reserved 8 : reference buffer output 9 : reference divider output 10 : vco divider output 11: modulator clock from vco divider 12: auxiliary clock 13: auxiliar y spi clock 14: auxiliary spi enable 15: auxiliary spi data output 16: pd down 17: pd up 18: internal clock path ( sd3 ) clock delay 19: sd3 core clock 20: autostrobe integer write 21: autostrobe fracti onal write 22: autostrobe auxiliary spi 23: spi latch enable 24: vco divider sync reset 25: seed load strobe 26 to 29: not used 30: spi output buffer enable 31: soft reset , rst 5 r/w gpo te st data 1 0 1 : gpo test data 6 r/w prevent a utomux sdo 1 0 1 : o utputs gpo data only 0 : automuxes between sdo and gpo data 7 r/w ldo driver always on 1 0 1 : ld/sdo pin driver always on 0 : ld/sdo pin driver only on during spi read cycle 8 r/w disable pfet 1 0 0: enable ld/sdo pin high drive 1 : disable ld/sdo pin high drive 9 r/w disable nfet 1 0 0: enable ld/sdo pin low drive 1 : disable ld/sdo pin low drive
data sheet HMC832A rev. b | page 41 of 48 vco tune register the vco tune register is a read only register. table 29. register 0x 10, vco tune register (default 0x 000020) bit type name width default description 7:0 r v co switch setting 8 32 indicates the vco switch setting selected by the a utocalibration state machine to yield the nearest free running vco frequency to the desired operating frequency. not valid when reg ister 0x 10[8] = 1, a utocalibration b usy. w hen a manual change is made to the vco switch settings , this register does not indicate the current vco switch position. vco subsystems ma y not use all the msbs, in which case the unused bits are dont care bits . 0 = highest frequency . 1 = second highest frequency . 255 = lowest frequency . 8 r autocalibration b usy 1 0 busy when the a utocalibration state machine is searching for the nearest switch setting to the requested frequency. sucessive approximat ion register the successive approximation register ( sar ) is a read only register. table 30. register 0x 11, successive approximation register (default 0x 07ffff) bit type name width default description 18:0 r sar error magnitude counts 19 2 19 to 1 sar error magnitude counts 19 r sar error sign 1 0 sar error sign 0 = error is positive 1 = error is negative general - purpose 2 regis ter the gpo 2 register is a read only register. table 31. register 0x 12, gpo2 register (default 0x 000000) bit type name width default description 0 r gpo 1 0 gpo s tate 1 r lock d etect 1 0 lock detect status 1 = locked 0 = unlocked built - in self test (bist) register the bist register is a read only register. table 32. register 0x 13, bist register (default 0x 001259) bit type name width default description 16:0 r reserved 17 4697 d reserved
HMC832A data sheet rev. b | page 42 of 48 vco subsystem register m ap t he vco subsystem uses indirect addressing via register 0x 05. for more detailed information on how to write to the vco subsystem , see the vco serial port interface (vspi) section . the vco tu ning register is write only. table 33. vco_reg 0x 00 , tuning register bit type name width default description 0 w c al 1 0 vco tune voltage is redirected to a temperature compensated calibration voltage 8:1 w caps 8 16 vco sub band s election 0000 0000: maximum frequency 1111 1111: minimum frequency vco enable register the vco enable register is a write only register. table 34. vco_reg 0x 01 , enable register bit type name width default description 0 w master e nable vco s ubsystem 1 1 0 : a ll vco subsystem blocks are turned o ff. 1 w vco e nable 1 1 enables vcos . 2 w pll buffer enable 1 1 enables pll b uffer to n d ivider . 3 w i nput/output master enable 1 1 enables output stage and the output divider . it does not enable/disable the vco. 4 w reserved 1 1 reserved . 5 w output stage enable 1 1 output stage enabl e . 7:6 w reserved 2 3 reserved . 8 w reserved 1 1 reserved . example: disabling the output s tage of the vco subsystem to disable the output sta ge of the vco subsystem of the HMC832A , clear bit 5 in vco_reg 0x01. if the other bits are left unchanged, write 1 1101 1111 into vco_reg 0x01. the vco subsystem register is accessed via a write to pll subsystem register 0 x 05 = 1 1101 1111 0001 00 = 0 xef 88. register 0x05[2:0] = 000 b ; vco subsystem id 0 . register 0x05[6:3] = 0001 b ; vco subsystem register address. register 0x05[7] = 1 b ; master enable. register 0x05[8] = 1 b ; vco enable. register 0x0 5[9] = 1 b ; pll buffer enable. register 0x05[10] = 1 b ; i/o master enable. register 0x05[11] = 1 b ; reserved. register 0x05[12] = 0 b ; disable the output stage. register 0x05[14:13] = 11 b ; reserved. register 0x05[15] = 1 b ; dont care.
data sheet HMC832A rev. b | page 4 3 of 48 vco output divider r eg ister this is a write only register. t o write 0 1111 1110 into vco_reg 0x02 (vco_id = 000b) and set the vco output divider to divide by 62, the following must be written to register 0x05 = 0 1111 1110 0010 000: register 0 x 05[ 2:0 ] = 000 ; subsystem id 0 regi ster 0 x 05[ 6:3 ] = 0010 ; vco register address 2 d. register 0x05[16:7] = 0 1111 1110 ; divide by 62 , maximum output rf gain. table 35. vco_reg 0x 02 , output divider register bit type name width default description 5:0 w rf d ivide ratio 6 1 0 : mutes the output when vco_reg 0x 03 [ 8:7 ] = 0 d 1: f o 2: f o / 2 3 : invalid, defaults to 2 4: f o / 4 5 : invalid, defaults to 4 6: f o / 6 60: f o / 60 61 : invalid, defaults to 60 62: f o /62 > 62 invalid, defaults to 62 8:6 w reserved 3 0 reserved vco configuration re gister the vco configuration register is a write only register. table 36. vco_reg 0x 03 , config uration register bit type name width default description 1: 0 w programmable performance mode 2 2 selects the output noise floor performance level at a cost of increased current consumption . 01 : low current consumption mode. 11 : high performance mode. other states ( 00 and 10 ) not supported. 2 w rf_n output enable 1 0 enables the output on rf_n pin. required for differential operation, or single - ended output on the rf_n pin. 3 w rf_p output enable 1 0 enables the output on rf_p pin. required for differential operation, or single - ended output on the rf_p pin. 4 w reserved 1 1 reserved . 5 w return l oss 1 0 0: return loss = ? 5 db t ypical ( h ighest output power) . 1 : return loss = ? 10 db typical. 6 w reserved 1 0 reserved . 8:7 w mute m ode 2 1 defines when the mute function is enabled (the output is muted), see the vco output mute function section and figure 35 for more information . 00: enables mute when the divide ratio , vco_reg 0x02[5:0] = 0. this enables the HMC832A to be backward compatible to the hmc830 mute function. 01: during vco calibration (s ee the vco calibration section for more details). 10: n ot su pported . 11: m ute all rf outputs (unconditional) .
HMC832A data sheet rev. b | page 44 of 48 vco calibration/bias , center frequency calibration (cf_cal) , and msb calibratio n registers these registers are write only. s pecified performance is only guaranteed with the required settings in table 37 only; other settings are not supported. table 37. vco_reg 0x 04 , c alibration /bias register bit type name width default description 0 w initialization 9 201 d reserved table 38. vco_reg 0x 05 , cf_ cal register bit type name width default description 8:0 w reserved 9 170 d reserved table 39. vco_reg 0x 06 , msb cal ibration register bit type name width default description 8:0 w reserved 9 255d reserved vco output power con trol the vco power control register is write only. table 40. vco_reg 0x 07 , output power control register bit type name width default description 3:0 w output stage gain control 4 1 output stage gain control in 1 db steps 0d: 0 db gain 1d: 1 db gain 2d: 2 db gain 10d: 10 db gain 11d: 11 db gain 4 w initialization 1 0 program to 1 d 8:5 w reserved 4 4 d program to 4 d
data sheet HMC832A rev. b | page 45 of 48 evaluation p rinted c ircuit b oard (pcb) th e circuit board used in the application use s rf circuit design techniques. signal lines have 50 ? impedance , whereas the package ground leads and exposed pad ar e connected directly to the ground plane similar to that shown in figure 53 and figure 54. use a sufficient number of via holes t o connect the top and bottom ground planes. the evaluation circuit board shown figure 53 and figure 54 is available from analog devices upon request. figure 53 . silk s creen and pcb traces top layer figure 54 . silk s creen and pcb traces bottom layer 600-00581-00-1 ref in n l ock detect usb gnd sck sdi sdo sen ad4 vcccp p +3.3v gnd vcc1 d0 d1 tpll/ t c x o 5.5v tp1 tp3 tp2 tp4 c14 c5 c40 c28 c10 c20 c23 c26 c24 c15 c18 c22 c27 c19 c37 c38 c6 c11 c12 c39 c41 c25 c21 c13 c16 c9 r8 r16 r10 r28 r1 r20 r25 r18 r14 r29 r5 r19 r12 r9 r27 r7 j3 j4 j5 r11 r15 r37 u1 tp5 c29 c30 c31 c32 c35 c44 c45 c33 c34 u3 d1 r17 r21 r22 r23 r24 r26 r31 r32 r33 r34 r35 r36 r38 sw1 l1 r13 r6 r39 r40 r41 r42 c17 c42 c46 c7 r43 u2 y1 c48 c49 c50 c51 c52 c54 c55 c47 u4 r46 r47 r48 r49 c53 c8 jp1 jp2 jp3 jp4 jp5 r44 r45 r50 c56 HMC832A l o t xxx 13 1 10-039 13 1 10-139 c3 c2 c1 c4 c36 r3 r2 r4 r30 j7 c43 a1
HMC832A data sheet rev. b | page 46 of 48 changing evaluation board reference frequency and cp current configura tion the evaluation boa rd is provided with a 50 mhz on - board reference oscillator, and type 1 loop filter configuration , as shown in figure 52 (~127 khz bandwidth , see table 13 ). the default reg ister configuration file included in the analog devices pll e valuation software sets the comparison frequency to 50 mhz (r = 1, that is, register 0x 02 = 1 ). as with all pll s and pll with i ntegrated vcos, modifying the comparison frequency or cp current res ult s in changes to the loop dynamics and ultimately, phase noise performance. when making these changes , keep in mind the following: ? cp offset current set ting . r efer to the charge pump (cp) and phase detector (pd) section . ? ld c onfiguration . r efer to the lock detect section . to redesign the loop filter for a particular application, download the pll d esign software tool , adisimpll ?. the analog devices pll d esign enables users to accurately model and analyze performance of all analog devices plls, plls with i ntegrated vcos, and clock generators . it supports various loop filter topologies, and enables users to design custom loop filters and accurately simulate resulting performance. for more information, see the loop filter and frequency changes section. for evaluation purposes, the HMC832A evaluation board is shipped with an on - board, low cost, low noise (100 ppm), 50 mhz vcxo, enabling evaluation of most parameters including phase noise without any external references. exact phase or frequency measurements require the HMC832A to use the same reference as the measuring instrument. to accommodate this requirement, the HMC832A evaluation board inc ludes the hmc1031 ; a simple low current integer - n pll that can lock the on - board vcxo to an external 10 mhz reference input commonly provided by most test equipment. to lock the HMC832A to an external 10 mhz reference , connect the external reference output to the j5 input of the HMC832A evaluation board and change the hmc1031 integer divider value to 5 by changing the switch settings , d1 = 1 (sw1 to sw 4 closed), and d0 = 0 (sw2 to sw 3 open). fo r more information , see the hmc1031 data sheet. evaluation kit conte nts the evaluation kit contains one ev1 HMC832A lp6g evaluation pcb, a usb interface board, a six - foot usb type a male to usb type b femal e cable, a cd rom that contains the user manual, evaluation pcb schematic, evaluation software , and analog devices pll design software. to order the evaluation kit, see the ordering guide section for the product nu mber.
data sheet HMC832A rev. b | page 47 of 48 outline dimensions figure 55 . 40 - lead lead frame chip scale package [ lfcsp_vq] 6 mm 6 mm body, very thin quad (hcp - 40 - 1) dimensions shown in millimeters figure 56 . tape and reel outline dimens ions dimensions shown in millimeters 03-31-2015- a 0.50 bsc bottom view top view pin 1 indic a t or exposed pad pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref 4.50 ref coplanarity 0.08 0.30 0.25 0.20 6.10 6.00 sq 5.90 0.90 0.85 0.80 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.35 0.30 0.25 0.20 min 4.75 4.70 sq 4.65 compliant to jedec standards mo-220 40 1 11 10 20 21 30 31 04-01-2015- a
HMC832A data sheet rev. b | page 48 of 48 ordering guide model 1 lead finish msl rating temperature range package description package option qty. brand 2 HMC832Alp6ge 100% matte sn msl 1 ? 40 c to + 85 c 40 - lead lead frame chip scale package [lfcsp_vq] hcp -4 0 -1 h 832 xxxx a HMC832Alp6getr 100% matte sn msl 1 40 c to + 85 c 40 - lead lead frame chip scale package [lfcsp_vq], 7? tape and reel hcp -40 -1 500 h 832 xxxx a ek1HMC832Alp6g evaluation kit ev1HMC832Al p6g evaluation board 1 e = rohs compliant part. 2 four - digit lot number xxxx. ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13110 - 0 - 11/15(b)

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